Display driver circuit, display module, method for driving display, and electronic device

Abstract

An electronic device includes a display including a first display area and a second display area. The electronic device further includes a main controller configured to send a first clock signal separately to a first display driver circuit and a second display driver circuit. The first display driver circuit is configured to receive the first clock signal and to output a first GOA clock signal to the display. The first GOA clock signal is generated based on the first clock signal. The second display driver circuit is configured to receive the first clock signal, and is further configured to output a second GOA clock signal to the display. The second GOA clock signal is generated based on the first clock signal.

What is claimed is: 
     
       1. An electronic device, comprising:
 a display comprising a first display area and a second display area; 
 a first display driver circuit coupled to the display and comprising:
 a first clock receive end; and 
 a first gate driver on array (GOA) clock signal output end configured to output a first GOA clock signal to the display, wherein the first GOA clock signal is configured to control a GOA of the first display area to be enabled or disabled; 
 
 a second display driver circuit coupled to the display and comprising:
 a second clock receive end; and 
 a second GOA clock signal output end configured to output a second GOA clock signal to the display, wherein the second GOA clock signal is configured to control a GOA of the second display area to be enabled or disabled; and 
 
 a main controller coupled to the first display driver circuit and the second display driver circuit and comprising a first clock output end configured to send a first clock signal separately to the first display driver circuit and the second display driver circuit, wherein the first clock receive end is configured to receive the first clock signal, wherein the first GOA clock signal is based on the first clock signal, wherein the second clock receive end is configured to receive the first clock signal, and wherein the second GOA clock signal is based on the first clock signal. 
 
     
     
       2. The electronic device of  claim 1 , wherein the first display driver circuit further comprises a first vertical synchronization signal output end configured to output a first vertical synchronization signal to the display to perform frame synchronization on the first display area, wherein the first vertical synchronization signal is based on the first clock signal, wherein the second display driver circuit further comprises a second vertical synchronization signal output end configured to output a second vertical synchronization signal to the display to perform frame synchronization on the second display area, wherein the second vertical synchronization signal is based on the first clock signal, and wherein the first vertical synchronization signal and the second vertical synchronization signal have a same phase. 
     
     
       3. The electronic device of  claim 1 , wherein the first display driver circuit further comprises a first horizontal synchronization signal output end configured to output a first horizontal synchronization signal to the display to perform row synchronization on the first display area, wherein the first horizontal synchronization signal is based on the first clock signal, wherein the second display driver circuit further comprises a second horizontal synchronization signal output end configured to output a second horizontal synchronization signal to the display to perform row synchronization on the second display area, and wherein the second horizontal synchronization signal is based on the first clock signal. 
     
     
       4. The electronic device of  claim 1 , wherein the first display driver circuit further comprises a first emission (EM) signal output end configured to output a first EM signal to the display to control a pixel circuit in the first display area to emit light or not to emit light, wherein the first EM signal is based on the first clock signal, wherein the second display driver circuit further comprises a second EM signal output end configured to output a second EM signal to the display to control a pixel circuit in the second display area to emit light or not to emit light, and wherein the second EM signal is based on the first clock signal. 
     
     
       5. The electronic device of  claim 1 , wherein the first display driver circuit further comprises:
 an internal clock generation module configured to generate a second clock signal; and 
 a video processing module that comprises a digital circuit and an analog circuit and is configured to process video data from the main controller to generate a video source signal to be sent to the display, wherein a first reference clock of the digital circuit is based on the second clock signal, and wherein a second reference clock of the analog circuit is based on the first clock signal. 
 
     
     
       6. The electronic device of  claim 5 , wherein the video processing module further comprises a buffer disposed between the digital circuit and the analog circuit in the video processing module. 
     
     
       7. The electronic device of  claim 6 , wherein the buffer is configured to compensate for a timing error between the first reference clock and the second reference clock. 
     
     
       8. The electronic device of  claim 1 , wherein the display comprises a flexible display. 
     
     
       9. A display driver circuit, comprising:
 a first clock receive end configured to receive a first clock signal from a main controller; 
 a first gate driver on array (GOA) clock signal output end configured to output a first GOA clock signal to a display to control a GOA of the display to be enabled or disabled, wherein the first GOA clock signal is based on the first clock signal; 
 an internal clock generation module configured to generate a second clock signal; and 
 a video processing module comprising a digital circuit and an analog circuit and configured to process video data from the main controller to generate a video source signal to be sent to the display, wherein a first reference clock of the digital circuit is based on the second clock signal, and wherein a second reference clock of the analog circuit is based on the first clock signal. 
 
     
     
       10. The display driver circuit of  claim 9 , wherein the display driver circuit further comprises a first vertical synchronization signal output end configured to output a first vertical synchronization signal to the display to perform frame synchronization on the display, and wherein the first vertical synchronization signal is based on the first clock signal. 
     
     
       11. The display driver circuit of  claim 9 , wherein the display driver circuit further comprises a first horizontal synchronization signal output end configured to output a first horizontal synchronization signal to the display to perform row synchronization on the display, and wherein the first horizontal synchronization signal is based on the first clock signal. 
     
     
       12. The display driver circuit of  claim 9 , wherein the display driver circuit further comprises a first emission (EM) signal output end configured to output a first EM signal to the display to control a pixel circuit in the display to emit light or not to emit light, and wherein the first EM signal is based on the first clock signal. 
     
     
       13. The display driver circuit of  claim 9 , wherein the video processing module further comprises a buffer disposed between the digital circuit and the analog circuit. 
     
     
       14. The display driver circuit of  claim 13 , wherein the buffer is configured to compensate for a timing error between the first reference clock and the second reference clock. 
     
     
       15. A method for driving a display of an electronic device, wherein the method comprises:
 sending, by a main controller, a first clock signal separately to a first display driver circuit of the electronic device and a second display driver circuit of the electronic device; 
 outputting, by the first display driver circuit, a first gate driver on array (GOA) clock signal to the display to control a GOA of a first display area of the display to be enabled or disabled, wherein the first GOA clock signal is based on the first clock signal; and 
 outputting, by the second display driver circuit, a second GOA clock signal to the display to control a GOA of a second display area of the display to be enabled or disabled, wherein the second GOA clock signal is based on the first clock signal. 
 
     
     
       16. The method of  claim 15 , further comprising:
 outputting, by the first display driver circuit, a first vertical synchronization signal to the display to perform frame synchronization on the first display area, wherein the first vertical synchronization signal is based on the first clock signal; and 
 outputting, by the second display driver circuit, a second vertical synchronization signal to the display to perform frame synchronization on the second display area, wherein the second vertical synchronization signal is based on the first clock signal, and wherein the first vertical synchronization signal and the second vertical synchronization signal have a same phase. 
 
     
     
       17. The method of  claim 15 , further comprising:
 outputting, by a first horizontal synchronization signal output end of the first display driver circuit, a first horizontal synchronization signal to the display to perform row synchronization on the first display area, wherein the first horizontal synchronization signal is based on the first clock signal; and 
 outputting, by a second horizontal synchronization signal output end of the second display driver circuit, a second horizontal synchronization signal to the display to perform row synchronization on the second display area, wherein the second horizontal synchronization signal is based on the first clock signal. 
 
     
     
       18. The method of  claim 15 , further comprising:
 outputting, by a first emission (EM) signal output end of the first display driver circuit, a first EM signal to the display to control a pixel circuit in the first display area to emit light or not to emit light, wherein the first EM signal is based on the first clock signal; and 
 outputting, by a second EM signal output end of the second display driver circuit, a second EM signal to the display to control a pixel circuit in the second display area to emit light or not to emit light, wherein the second EM signal is based on the first clock signal. 
 
     
     
       19. The method of  claim 15 , further comprising:
 generating, by an internal clock generation module in the first display driver circuit, a third clock signal; and 
 processing, by a video processing module of the first display driver circuit, video data input from the main controller to generate a video source signal to be sent to the display, wherein a first reference clock of a digital circuit in the video processing module is based on the third clock signal, and wherein a second reference clock of an analog circuit in the video processing module is based on the first clock signal. 
 
     
     
       20. The method of  claim 19 , further comprising compensating, by a buffer disposed in the video processing module between the digital circuit and the analog circuit, for a timing error between the first reference clock and the second reference clock.