Methods and apparatus for scribe seal structures

Abstract

An example integrated circuit die includes: lower level conductor layers, lower level insulator layers between the lower level conductor layers, lower level vias extending vertically through the lower level insulator layers, upper level conductor layers overlying the lower level conductor layers, upper level insulator layers between and surrounding the upper level conductor layers, upper level vias; at least two scribe seals arranged to form a vertical barrier extending vertically from the semiconductor substrate to a passivation layer at an upper surface of the integrated circuit die; and at least one opening extending vertically through one of the at least two scribe seals and extending through: the upper level conductor layers, the upper level via layers, the lower level conductor layers, and the lower level via layers.

What is claimed is: 
     
       1. An integrated circuit die having opposing first and second sides, the integrated circuit die comprising:
 a passivation layer at the first surface; 
 a semiconductor substrate at the second surface, the substrate having a first conductivity type; 
 a first scribe seal at an exterior periphery of the die; 
 a second scribe seal concentric with and interior to the first scribe seal; 
 a conductive coil spaced from and interior to the second scribe seal, the conductive coil coupled to a voltage supply terminal configured to supply current through the coil; 
 a voltage controlled oscillator (VCO), the VCO including the conductive coil; 
 the first and second scribe seals extending from the semiconductor substrate to an upper level passivation layer; 
 the first and second scribe seals including respective lower level conductor layers, lower level vias, upper level conductor layers and upper level vias, the lower level conductor layers overlying the semiconductor substrate, and the upper level conductor layers overlying the lower level conductor layers; 
 lower level insulator layers between and surrounding the lower level conductor layers, the lower level vias extending through ones of the lower level insulator layers and coupling ones of the lower level conductor layers; 
 a ground strap coupled between at least one of the lower level conductor layers and a ground terminal; 
 upper level insulator layers between and surrounding the upper level conductor layers, the upper level vias extending through ones of the upper level insulator layers and electrically coupling ones of the upper level conductor layers; 
 the first scribe seal having a first opening along the first side of the integrated circuit die, the first opening extending through the first scribe seal's upper level conductor layers, upper level via layers, lower level conductor layers and lower level via layers; 
 the second scribe seal having a second opening along the second side of the integrated circuit die, and the second opening being opposite the first opening and extending through the second scribe seal's upper level conductor layers, upper level via layers, lower level conductor layers and lower level via layers; 
 a first doped diffusion region in the semiconductor substrate, the first doped diffusion region having a first concentration of a second conductivity type different from the first conductivity type; 
 a second doped diffusion region in the semiconductor substrate, the second doped diffusion region surrounding the first doped diffusion region and having a second concentration of the second conductivity type, the second concentration being less than the first concentration; and 
 the first scribe seal includes a lower level via that contacts the first doped diffusion region. 
 
     
     
       2. The integrated circuit die of  claim 1 , wherein the coil is a first coil, and is inductively coupled to a second coil. 
     
     
       3. The integrated circuit die of  claim 2 , wherein the first coil is configured to transmit or receive electromagnetic communication signals from the second coil. 
     
     
       4. The integrated circuit die of  claim 1 , wherein the first coil is adapted to be coupled to a capacitor, resulting in an oscillator circuit. 
     
     
       5. The integrated circuit die of  claim 1 , wherein the first conductivity type is P type, and the second conductivity type is N type. 
     
     
       6. The integrated circuit die of  claim 1 , wherein the first conductivity type is N type, and the second conductivity type is P type.