Shift register circuit

Abstract

A display device including a bidirectional shift register circuit, including: a plurality of cascade-connected register circuits; various circuits for setting various nodes to various voltage levels responsive to various signals input to various terminals; and an output circuit which outputs the clock pulse as an output pulse when the voltage of the first node is high level, wherein, at the forward shift operation, the bottom dummy register circuit is not input the reset signal and the first node of the bottom dummy register circuit is reset if the initial reset circuit of the bottom dummy register circuit receives the backward trigger signal, and wherein, at the backward shift operation, the top dummy register circuit is not input the reset signal and the first node of the top dummy register circuit is reset if the initial reset circuit of the top dummy register circuit receives the forward trigger signal.

What is claimed is: 
     
       1. A shift register circuit comprising:
 four clock signal lines supplying four-phase clock pulses respectively; 
 a plurality of cascade-connected register circuits including a top register circuit, a bottom register circuit, and main register circuits providing between the top register circuit and the bottom register circuit; and 
 a forward scan signal line supplying a forward scan signal to the plurality of cascade-connected register circuits, wherein 
 each of the plurality of cascade-connected register circuits has
 a forward set terminal; 
 a reset terminal; 
 a first node; 
 a second node; 
 a second node reset terminal; 
 an output circuit which outputs one of the four-phase clock pulses when a voltage of the first node is an active level; 
 a second output circuit which output a non-active level voltage when a voltage of the second node is the active level; 
 a first node set circuit which sets a voltage of the first node to the active level when a set signal is input into the forward set terminal; 
 a second node set circuit which sets a voltage of the second node to the active level when other one of the four-phase clock pulses is input into the reset terminal; 
 a first node control circuit which sets the first node to the non-active level when a voltage of the second node is the active level; 
 a second node control circuit which sets the second node to the non-active level when a voltage of the first node is the active level; and 
 a second node reset circuit which sets the second node to the non-active level when a voltage of the second node reset terminal is the active level, 
 
 the forward scan signal sets the voltage of the first node of the top register circuit to the active level, and 
 the forward scan signal sets the voltage of the second node reset terminal of the bottom register circuit to the active level. 
 
     
     
       2. The shift register circuit according to  claim 1 , wherein
 the first node of the main register circuit is set by the output pulse from previous stage, and 
 the first node of the main register circuit is reset by the pulse signal which output pulse form subsequent stage. 
 
     
     
       3. The shift register circuit according to  claim 1 , wherein
 a period of one of the four-phase clock pulses does not overlap with a period of another one of the four-phase clock pulses. 
 
     
     
       4. The shift register circuit according to  claim 1 , further comprising a reverse scan signal line supplying a reverse scan signal to the plurality of cascade-connected register circuits, wherein
 each of the plurality of cascade-connected register circuits further includes a backward set terminal, and 
 the first node set circuit sets a voltage of a the first node to the active level when the set signal is input into the backward set terminal. 
 
     
     
       5. The shift register circuit according to  claim 4 , wherein
 a shift direction in the plurality of cascade-connected register circuits when the set signal is input into the backward set terminal is opposite to a shift direction in the plurality of cascade-connected register circuits when the set signal is input into the forward set terminal.