Vertical memory device including substrate control circuit and memory system including the same

Abstract

A nonvolatile memory device comprises a first semiconductor layer including, an upper substrate, and a memory cell array in which a plurality of word lines on the upper substrate extend in a first direction and a plurality of bit lines extend in a second direction. The nonvolatile memory device comprises a second semiconductor layer under the first semiconductor layer in a third direction perpendicular to the first and second directions, the second semiconductor layer including, a lower substrate, and a substrate control circuit on the lower substrate and configured to output a bias voltage to the upper substrate. The second semiconductor layer is divided into first through fourth regions, each of the first through fourth regions having an identical area, and the substrate control circuit overlaps at least a portion of the first through fourth regions in the third direction.

What is claimed is: 
     
       1. A nonvolatile memory device comprising:
 a first semiconductor layer including,
 an upper substrate including a well region, 
 a plate electrode of which a top surface contacts a bottom surface of the upper substrate, and 
 a memory cell array in which a plurality of word lines on the upper substrate extend in a first direction and a plurality of bit lines extend in a second direction; and 
 
 a second semiconductor layer under the first semiconductor layer in a third direction perpendicular to the first and second directions, the second semiconductor layer including,
 a lower substrate, and 
 a substrate control circuit on the lower substrate and configured to output a bias voltage to the upper substrate, 
 
 wherein the second semiconductor layer is divided into first through fourth regions, each of the first through fourth regions having an identical area, the substrate control circuit overlaps at least a portion of each of the first through fourth regions in the third direction, 
 each of the first through fourth regions of the second semiconductor layer comprises at least one respective substrate contact plug, 
 wherein at least one substrate contact plug includes a first substrate contact plug and a second substrate contact plug, 
 wherein the first substrate contact plug connects the well region of the upper substrate and the lower substrate, and the second substrate contact plug connects the plate electrode and the lower substrate, and 
 each of the first substate contact plugs directly connect to the well region of the upper substrate and has a sidewall having a straight and continuous profile, each of the second substrate contact plugs directly connect to the plate electrode and has a sidewall having a straight and continuous profile, and each of the first substrate contact plugs has a height greater than any of the second substrate contact plugs. 
 
     
     
       2. The nonvolatile memory device of  claim 1 , wherein the first and second regions are symmetrical about a boundary between the first and second regions. 
     
     
       3. The nonvolatile memory device of  claim 1 , wherein the plate electrode is formed between the second semiconductor layer and the upper substrate, the second substrate contact plug electrically connects the plate electrode to the substrate control circuit. 
     
     
       4. The nonvolatile memory device of  claim 3 , wherein the upper substrate, the plate electrode, and the second substrate contact plug each include polysilicon doped with an identical conductivity type. 
     
     
       5. The nonvolatile memory device of  claim 4 , wherein a doping concentration of the plate electrode and the second substrate contact plug is greater than a doping concentration of the upper substrate. 
     
     
       6. The nonvolatile memory device of  claim 3 , wherein the plate electrode and the second substrate contact plug comprise a metal material. 
     
     
       7. The nonvolatile memory device of  claim 1 , wherein at least a first through fourth area of the substrate control circuit respectively overlap the first through fourth regions, wherein the first through fourth area of the substrate control circuit are substantially identical. 
     
     
       8. The nonvolatile memory device of  claim 1 , wherein the substrate control circuit comprises a first sub-control circuit and a second sub-control circuit, wherein the first sub-control circuit overlaps the first and third regions in the third direction, and the second sub-control overlaps the second and fourth regions in the third direction, and
 the bias voltage corresponding to a voltage for programming or erasing at least one of the each cell in the memory cell array. 
 
     
     
       9. The nonvolatile memory device of  claim 1 , wherein the first and third regions are adjacent to each other in the first direction and the first and second region are adjacent to each other in the second direction. 
     
     
       10. The nonvolatile memory device of  claim 1 , wherein the memory cell array comprises a plurality of gate conductive layers stacked on the upper substrate, and a plurality of channel layers penetrating the plurality of gate conductive layers and extending in a third direction perpendicular to the first and second directions. 
     
     
       11. The nonvolatile memory device of  claim 1 , wherein the substrate control circuit is at a center of an overlap region between the second semiconductor layer and the memory cell array. 
     
     
       12. The nonvolatile memory device of  claim 1 , wherein the substrate control circuit overlaps only one corner of each of the first through fourth regions. 
     
     
       13. A nonvolatile memory device comprising:
 a first semiconductor layer including an upper substrate, a plate electrode of which a top surface contacts a bottom surface of the upper substrate, and a memory cell array stacked on the upper substrate in a stacking direction; and 
 a second semiconductor layer under the first semiconductor layer in the stacking direction, the second semiconductor layer including a lower substrate, a plurality of substrate contact plugs between the lower substrate and the upper substrate, and a substrate control circuit on the lower substrate and configured to provide a bias voltage to the upper substrate through the plurality of substrate contact plugs, 
 wherein the second semiconductor layer is divided into first through fourth regions having an identical area and, in the stacking direction, the substrate control circuit overlaps at least a portion of at least two regions among the first through fourth regions, 
 wherein the plurality of substrate contact plugs include a first substrate contact plug and a second substrate contact plug, 
 wherein the first substrate contact plug connects a well region of the upper substrate and the lower substrate, wherein the second substrate contact plug connects the plate electrode and the lower substrate, and 
 each of the first substate contact plugs directly connect to the wall region of the upper substrate and has a sidewall having a straight and continuous profile, each of the second substrate contact plugs directly connect to the plate electrode and has a sidewall having a straight and continuous profile, and each of the first substate contact plus has a height greater than any of the second substrate contact plugs. 
 
     
     
       14. The nonvolatile memory device of  claim 13 , wherein the upper substrate comprises polysilicon doped with a first conductivity type, and the well region is doped with a second conductivity type opposite to the first conductivity type. 
     
     
       15. The nonvolatile memory device of  claim 14 ,
 wherein the first substrate contact plug penetrates a portion of the first semiconductor layer and a portion of the second semiconductor layer, electrically connects the well region to the lower substrate, is surrounded by an insulating pattern filling a hole through the upper substrate, and a configured to supply a voltage to a common source line. 
 
     
     
       16. The nonvolatile memory device of  claim 13 ,
 wherein a bottom surface of the plate electrode contacts a top surface of the second substrate contact plug. 
 
     
     
       17. A nonvolatile memory device comprising:
 a first semiconductor layer including,
 a memory cell array in which a plurality of word lines extend in a first direction and a plurality of bit lines extend in a second direction, 
 an upper substrate under the memory cell array, the upper substrate supporting the memory cell array and including a well region; and 
 a plate electrode of which a top surface contacts a bottom surface of the upper substrate; and 
 
 a second semiconductor layer under the first semiconductor layer in a third direction perpendicular to the first and second directions, the second semiconductor layer including
 a lower substrate, 
 a substrate control circuit on the lower substrate and configured to output a bias voltage to the upper substrate, and 
 
 a plurality of substrate contact plugs electrically connecting the upper substrate and the lower substrate to output the bias voltage to the upper substrate, 
 wherein the second semiconductor layer is divided by a first imaginary line in the first direction and a second imaginary line in the second direction which cross each other, and the second semiconductor layers comprises at least a portion of first through fourth regions overlapping the memory cell array, 
 wherein the plurality of substrate contact plugs include a first substrate contact plug and a second substrate contact plug, 
 wherein the first substrate contact plug connects the well region of the upper substrate and the lower substrate, 
 wherein the second substrate contact plug connects the plate electrode and the lower substrate, and 
 each of the first substate contact plugs directly connect to the wall region of the upper substrate and has a sidewall having a straight and continuous profile, each of the second substrate contact plugs directly connect to the plate electrode and has a sidewall having a straight and continuous profile, and each of the first substrate contact plugs has a height greater than any of the second substrate contact plugs. 
 
     
     
       18. The nonvolatile memory device of  claim 17 , wherein at least a first through fourth area of the substrate control circuit respectively overlap at least a portion of the first through fourth regions in the third direction. 
     
     
       19. The nonvolatile memory device of  claim 17 , wherein at least one substrate contact plug in the first region and at least one substrate contact plug in the second region are symmetric about a boundary between the first and second regions. 
     
     
       20. The nonvolatile memory device of  claim 17 , wherein the first through fourth regions have an identical area.