US11543843B2ActiveUtilityA1

Providing low power charge pump for integrated circuit

81
Assignee: SILICON LAB INCPriority: Feb 18, 2020Filed: Apr 14, 2021Granted: Jan 3, 2023
Est. expiryFeb 18, 2040(~13.6 yrs left)· nominal 20-yr term from priority
H02M 3/156H02M 3/073G05F 1/575H02M 1/088
81
PatentIndex Score
1
Cited by
21
References
18
Claims

Abstract

In one embodiment, an apparatus includes: an amplifier to compare a reference voltage to a feedback voltage and to output a comparison signal based on the comparison; a loop circuit coupled to the amplifier, where the loop circuit is to receive the comparison signal and provide a regulated voltage to the amplifier as the feedback voltage in a first mode of operation, and in a second mode of operation to provide a predetermined feedback ratio point to the amplifier as the feedback voltage; and an output device coupled to the amplifier. The output device may be configured to receive a supply voltage and the comparison signal and output the regulated voltage at an output node based at least in part on the comparison signal.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
       1. An apparatus comprising:
 an amplifier to compare a reference voltage to a feedback voltage and to output a comparison signal based on the comparison; 
 a loop circuit coupled to the amplifier, wherein the loop circuit comprises:
 a voltage divider coupled to an output node, the voltage divider to provide the feedback voltage to the amplifier; 
 a current sensor to sense a current at the output node, the current sensor to provide the sensed current to the amplifier; and 
 a feedback capacitor coupled between the output node and the amplifier to provide a feedback path to the amplifier; and 
 
 an output device coupled to the amplifier, wherein the output device is to receive the comparison signal and a supply voltage and to output a regulated voltage at the output node based at least in part on the comparison signal. 
 
     
     
       2. The apparatus of  claim 1 , wherein the apparatus comprises a voltage regulator. 
     
     
       3. The apparatus of  claim 1 , further comprising a level shifter circuit coupled to the output node, wherein the level shifter circuit is to receive the regulated voltage and output a level shifted voltage. 
     
     
       4. The apparatus of  claim 3 , further comprising:
 a second output device coupled to the level shifter circuit to receive the level shifted voltage and output a first regulated voltage to a first load circuit; and 
 a third output device coupled to the level shifter circuit to receive the level shifted voltage and output a second regulated voltage to a second load circuit, wherein the regulated voltage and the first regulated voltage are at a first voltage level and the second regulated voltage is at a second voltage level. 
 
     
     
       5. The apparatus of  claim 4 , wherein:
 the output device is to output the regulated voltage in a snooze mode; 
 the second output device is to output the first regulated voltage in the snooze mode; and 
 the third output device is to output the second regulated voltage in the snooze mode. 
 
     
     
       6. A voltage regulator comprising:
 an amplifier to compare a reference voltage to a feedback voltage and to output a comparison signal based on the comparison; 
 a first loop circuit coupled to the amplifier, the first loop circuit comprising a fixed closed loop circuit having a voltage divider coupled to an output node, the voltage divider to provide the feedback voltage to the amplifier from a feedback node coupled between a first resistor and a second resistor; 
 a second loop circuit coupled to the amplifier, the second loop circuit comprising:
 a current sensor to sense a current at the output node, the current sensor to provide the sensed current to the amplifier; and 
 a feedback capacitor coupled between the output node and the amplifier to provide a feedback path to the amplifier; and 
 
 an output device coupled to the amplifier, wherein the output device is to receive the comparison signal and a supply voltage and output a regulated voltage at the output node based at least in part on the comparison signal. 
 
     
     
       7. The voltage regulator of  claim 6 , wherein the second loop circuit comprises an Ajuha loop. 
     
     
       8. The voltage regulator of  claim 6 , further comprising a level shifter circuit coupled to the output node, wherein the level shifter circuit is to receive the regulated voltage and output a level shifted voltage. 
     
     
       9. The voltage regulator of  claim 8 , further comprising:
 a second output device coupled to the level shifter circuit to receive the level shifted voltage and output a first regulated voltage to a first load circuit; and 
 a third output device coupled to the level shifter circuit to receive the level shifted voltage and output a second regulated voltage to a second load circuit. 
 
     
     
       10. The voltage regulator of  claim 9 , wherein the regulated voltage and the first regulated voltage are at a first voltage level and the second regulated voltage is at a second voltage level. 
     
     
       11. The voltage regulator of  claim 9 , wherein the first load circuit comprises high voltage circuitry. 
     
     
       12. The voltage regulator of  claim 9 , wherein the second load circuit comprises a flash memory. 
     
     
       13. The voltage regulator of  claim 6 , wherein the voltage regulator is to output the regulated voltage during a snooze mode. 
     
     
       14. An apparatus comprising:
 an amplifier to compare a reference voltage to a feedback voltage and to output a comparison signal based on the comparison; 
 a first loop circuit coupled to the amplifier, the first loop circuit comprising a fixed closed loop circuit having a voltage divider coupled to an output node, the voltage divider to provide the feedback voltage to the amplifier from a feedback node coupled between a first resistor and a second resistor; 
 a second loop circuit coupled to the amplifier, the second loop circuit comprising:
 a current sensor to sense a current at the output node, the current sensor to provide the sensed current to the amplifier; and 
 a feedback capacitor coupled between the output node and the amplifier; 
 
 an output device coupled to the amplifier, wherein the output device is to receive the comparison signal and a supply voltage and output a regulated voltage at the output node based at least in part on the comparison signal; 
 a level shifter circuit coupled to the output node, wherein the level shifter circuit is to receive the regulated voltage and output a level shifted voltage; 
 a second output device coupled to the level shifter circuit to receive the level shifted voltage and output a first regulated voltage to a first load circuit; and 
 a third output device coupled to the level shifter circuit to receive the level shifted voltage and output a second regulated voltage to a second load circuit. 
 
     
     
       15. The apparatus of  claim 14 , wherein the first load circuit comprises high voltage circuitry. 
     
     
       16. The apparatus of  claim 15 , wherein the second output device is to output the first regulated voltage to the first load circuit at a level less than approximately 2.4 volts. 
     
     
       17. The apparatus of  claim 14 , wherein the second load circuit comprises a flash memory. 
     
     
       18. The apparatus of  claim 14 , wherein the apparatus is to output the regulated voltage during a snooze mode.

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