Energy-efficient signal processing

Abstract

In some embodiments, an apparatus includes first and second signal processing circuitry configured to perform signal processing operations and second signal processing circuitry configured to perform signal processing operations, wherein the second signal processing circuitry includes a smaller amount of processing resources than the first signal processing circuitry. In some embodiments, the apparatus includes one or more storage elements configured to store context information for the second signal processing circuitry and the one or more storage elements are accessible to the first signal processing circuitry. The apparatus may be configured to select one of the first and second signal processing circuitry based on the complexity of input problems, the amount of transmission resources assigned to the apparatus, etc. In some embodiments, intermediate results of from the second signal processing circuitry are used as inputs to an operation performed by the first signal processing circuitry.

What is claimed is: 
     
       1. An apparatus, comprising:
 first circuitry configured to perform a frequency transform computation; 
 second circuitry configured to perform the frequency transform computation, wherein the second circuitry includes a smaller amount of processing resources than the first circuitry, wherein the second circuitry is configured to begin performing the frequency transform computation on at least a portion of a set of input data while the first circuitry is in a low power state; 
 one or more storage elements configured to store context information for the second circuitry, wherein the context information includes outputs from the frequency transform computation performed on the at least a portion of the set of input data, including, wherein the one or more storage elements are accessible to the first circuitry; and 
 circuitry configured to, based on the at least a portion of the set of input data, activate the first circuitry to resume and complete the frequency transform computation, wherein the completion uses the outputs of the frequency transform computation performed by the second circuitry, included in the context information, as an intermediate result; 
 wherein the outputs from the frequency transform computation in the context information include first frequency transform results for one or more first frequency transforms, wherein the one or more first frequency transforms are smaller than one or more second frequency transforms performed by the second circuitry to complete the frequency transform computation. 
 
     
     
       2. The apparatus of  claim 1 , wherein frequency transform computation includes a matrix multiplication. 
     
     
       3. The apparatus of  claim 2 , wherein the context information includes a result for a portion of an input matrix. 
     
     
       4. The apparatus of  claim 1 , wherein the frequency transform is a Fourier transform. 
     
     
       5. The apparatus of  claim 1 , wherein the apparatus is configured to operate in at least three modes of operation, at different times, including:
 a first mode of operation in which the first circuitry is in a low-power mode and the second circuitry is active; 
 a second mode of operation in which the second circuitry is in a low-power mode and the first circuitry is active; and 
 a third mode of operation in which both the first circuitry and the second circuitry is active and configured to perform at least portions of the frequency transform computation in parallel. 
 
     
     
       6. The apparatus of  claim 5 , wherein the apparatus is configured to switch between ones of the first, second, and third modes based on communication resources allocated to the apparatus by a cellular base station. 
     
     
       7. The apparatus of  claim 1 , wherein the first circuitry operates on a greater supply voltage level than the second circuitry. 
     
     
       8. The apparatus of  claim 1 , wherein the first circuitry is configured to perform the frequency transform computation using circuitry with transistors that have greater leakage than transistors that the second circuitry is configured to use to perform the frequency transform computation. 
     
     
       9. The apparatus of  claim 1 , wherein the first circuitry includes a higher-performance processor than the second circuitry. 
     
     
       10. The apparatus of  claim 1 , wherein the first circuitry includes at least one of:
 circuitry with lower memory access times than the second circuitry; 
 a greater amount of circuit area than the second circuitry; or 
 a greater number of input ports than the second circuitry. 
 
     
     
       11. The apparatus of  claim 1 , wherein the frequency transform computation is a portion of a decoding process for a wirelessly received message. 
     
     
       12. The apparatus of  claim 1 , wherein the frequency transform computation is part of signal processing of transmitted or received wireless signals. 
     
     
       13. The apparatus of  claim 1 , wherein the apparatus is a computing device that further comprises:
 a display; and 
 one or more wireless radios. 
 
     
     
       14. A method, comprising:
 performing, by second circuitry, a frequency transform computation, wherein the second circuitry includes a smaller amount of processing resources than first circuitry, wherein the second circuitry begins performing the frequency transform computation on at least a portion of a set of input data while the first circuitry is in a low power state; 
 storing context information for the second circuitry in one or more storage elements that are accessible to the first circuitry, wherein the context information includes outputs from the frequency transform computation performed on the at least a portion of the set of input data; and 
 activating the first circuitry to complete the frequency transform computation, based on the at least a portion of the set of input data, wherein the completing uses the outputs of the frequency transform computation performed by the second circuitry, included in the context information, as an intermediate result; 
 wherein the outputs from the frequency transform computation in the context information include first frequency transform results for one or more first frequency transforms, wherein the one or more first frequency transforms are smaller than one or more second frequency transforms performed by the second circuitry to complete the frequency transform computation. 
 
     
     
       15. The method of  claim 14 , wherein the frequency transform computation includes a matrix multiplication. 
     
     
       16. A non-transitory computer readable storage medium having stored thereon design information that specifies a design of at least a portion of a hardware integrated circuit in a format recognized by a semiconductor fabrication system that is configured to use the design information to produce the circuit according to the design, including:
 first circuitry configured to perform a frequency transform computation; 
 second circuitry configured to perform the frequency transform computation, wherein the second circuitry includes a smaller amount of processing resources than the first circuitry, wherein the second circuitry is configured to begin performing the frequency transform computation on at least a portion of a set of input data while the first circuitry is in a low power state; 
 one or more storage elements configured to store context information for the second circuitry, wherein the context information includes outputs from the frequency transform computation performed on the at least a portion of the set of input data, wherein the one or more storage elements are accessible to the first circuitry; and 
 circuitry configured to, based on the at least a portion of the set of input data, activate the first circuitry to complete the frequency transform computation, wherein the completion uses the outputs of the frequency transform computation performed by the second circuitry, included in the context information, as an intermediate result; 
 wherein the outputs from the frequency transform computation in the context information include first frequency transform results for one or more first frequency transforms, wherein the one or more first frequency transforms are smaller than one or more second frequency transforms performed by the second circuitry to complete the frequency transform computation. 
 
     
     
       17. The non-transitory computer readable storage medium of  claim 16 , wherein the frequency transform computation is a Fourier transform.