Neural network device, signal generation method, and program

Abstract

A neural network device includes a decimation unit configured to convert a discrete value of an input signal to a discrete value having a smaller step number than a quantization step number of the input signal on the basis of a predetermined threshold value to generate a decimation signal a modulation unit configured to modulate a discrete value of the decimation signal generated by the decimation unit to generate a modulation signal indicating the discrete value of the decimation signal, and a weighting unit including a neuromorphic element configured to output a weighted signal obtained by weighting the modulation signal through multiplication of the modulation signal generated by the modulation unit by a weight according to a value of a variable characteristic.

What is claimed is: 
     
       1. A neural network device comprising:
 a processor configured to:
 convert a discrete value of an input signal to a discrete value having a smaller step number than a quantization step number of the input signal based on a predetermined threshold value to generate a decimation signal; 
 modulate a discrete value of the decimation signal to generate a modulation signal indicating the discrete value of the decimation signal; and 
 output a weighted signal obtained by weighting the modulation signal through multiplication of the modulation signal by a weight according to a value of a variable characteristic with a neuromorphic element. 
 
 
     
     
       2. The neural network device according to  claim 1 , wherein the threshold value is determined based on a weighting result of the weighted signal. 
     
     
       3. The neural network device according to  claim 2 , wherein the processor is configured to perform pulse width modulation on the discrete value of the decimation signal to generate a pulse width modulation signal indicating the discrete value of the decimation signal using a pulse width. 
     
     
       4. The neural network device according to  claim 3 , wherein the processor is configured to:
 generate the decimation signals corresponding to a plurality of the respective input signals, and 
 generate the modulation signals corresponding to the plurality of respective decimation signals, with change timings of signal waveforms different from each other. 
 
     
     
       5. The neural network device according to  claim 2 , wherein the processor is configured to perform pulse frequency modulation on the discrete value of the decimation signal to generate a pulse frequency modulation signal indicating the discrete value of the decimation signal using a pulse frequency. 
     
     
       6. The neural network device according to  claim 5 , wherein the processor is configured to:
 generate the decimation signals corresponding to a plurality of the respective input signals, and 
 generate the modulation signals corresponding to the plurality of respective decimation signals, with change timings of signal waveforms different from each other. 
 
     
     
       7. The neural network device according to  claim 2 , wherein the processor is configured to:
 generate the decimation signals corresponding to a plurality of the respective input signals, and 
 generate the modulation signals corresponding to the plurality of respective decimation signals, with change timings of signal waveforms different from each other. 
 
     
     
       8. The neural network device according to  claim 2 , wherein the threshold value divides the quantization step number of the input signal into ranges having unequal widths. 
     
     
       9. The neural network device according to  claim 1 , wherein the processor is configured to perform pulse width modulation on the discrete value of the decimation signal to generate a pulse width modulation signal indicating the discrete value of the decimation signal using a pulse width. 
     
     
       10. The neural network device according to  claim 9 , wherein the processor is configured to:
 generate the decimation signals corresponding to a plurality of the respective input signals, and 
 generate the modulation signals corresponding to the plurality of respective decimation signals, with change timings of signal waveforms different from each other. 
 
     
     
       11. The neural network device according to  claim 1 , wherein the processor is configured to perform pulse frequency modulation on the discrete value of the decimation signal to generate a pulse frequency modulation signal indicating the discrete value of the decimation signal using a pulse frequency. 
     
     
       12. The neural network device according to  claim 11 , wherein the processor is configured to:
 generate the decimation signals corresponding to a plurality of the respective input signals, and 
 generate the modulation signals corresponding to the plurality of respective decimation signals, with change timings of signal waveforms different from each other. 
 
     
     
       13. The neural network device according to  claim 1 , wherein the processor is configured to:
 generate the decimation signals corresponding to a plurality of the respective input signals, and 
 generate the modulation signals corresponding to the plurality of respective decimation signals, with change timings of signal waveforms different from each other. 
 
     
     
       14. The neural network device according to  claim 1 , wherein the threshold value divides the quantization step number of the input signal into ranges having unequal widths. 
     
     
       15. The neural network device according to  claim 1 , wherein the processor is configured to:
 divide the quantization step number of the input signal into two to generate a binary decimation signal, 
 generate a binary modulation signal according to the decimation signal, 
 output the weighted signal obtained by weighting the binary modulation signal, and 
 detect a magnitude of a current of the weighted signal. 
 
     
     
       16. The neural network device according to  claim 1 , wherein the processor is further configured to:
 acquire the threshold value to be used for generation of the decimation signal. 
 
     
     
       17. The neural network device according to  claim 1 , wherein the threshold value is variably determined based on the input signal. 
     
     
       18. The neural network device according to  claim 1 , wherein a step number of the discrete value of the decimation signal is variably determined based on a value of the input signal in a range of the smaller step number than the quantization step number of the input signal. 
     
     
       19. A signal generation method comprising:
 converting a discrete value of an input signal to a discrete value having a smaller step number than a quantization step number of the input signal based on a predetermined threshold value to generate a decimation signal; 
 modulating a discrete value of the decimation signal to generate a modulation signal indicating the discrete value of the decimation signal; and 
 outputting a weighted signal in which the modulation signal is weighted by a neuromorphic element by multiplying the modulation signal by a weight according to a value of a variable characteristic. 
 
     
     
       20. A non-transitory computer readable medium storing a program for causing a computer included in a neural network device to execute:
 converting a discrete value of an input signal to a discrete value having a smaller step number than a quantization step number of the input signal based on a predetermined threshold value to generate a decimation signal; 
 modulating a discrete value of the decimation signal to generate a modulation signal indicating the discrete value of the decimation signal; and 
 supplying the modulation signal to a neuromorphic element that outputs a weighted signal obtained by weighting the modulation signal through multiplication of the modulation signal by a weight according to a value of a variable characteristic, to cause the weighted signal to be output.