Semiconductor device and manufacturing method of the semiconductor device

Abstract

A semiconductor device, and a method of manufacturing the semiconductor device, the method includes forming a first stack structure penetrated by first channel structures, forming electrode patterns surrounding second channel structures and separated from each other by first slits and second slits, the second channel structures coupled to the first channel structures, and the second slits comprising a different width from the first slits, filling each of the first slits and the second slits with an insulating material to cover sidewalk of the electrode patterns, and forming third slits passing through the insulating material in each of the second slits and extending to pass through the first stack structure.

What is claimed is: 
     
       1. A semiconductor device, comprising:
 a first gate stack structure including first interlayer insulating layers and first electrode patterns that are alternately stacked on each other; 
 second gate stack structures each including a second interlayer insulating layer and a second electrode pattern that are alternately stacked on the first gate stack structure; 
 slits defined between the second gate stack structures and overlapping the first gate stack structure, wherein the slits include a first slit and a second slit spaced apart from each other; 
 a vertical structure formed in the second slit and passing through the first gate stack structure; 
 a slit insulating layer between the vertical structure and a sidewall of the second slit; 
 first channel structures passing through the first gate stack structure; 
 second channel structures passing through each of the second gate stack structures and coupled to the first channel structures; and 
 a gate insulating layer between the second electrode pattern and each of the second channel structures and extending on a sidewall of the second interlayer insulating layer, 
 wherein the second channel structures farther protrude toward the first channel structures than the gate insulating layer. 
 
     
     
       2. The semiconductor device of  claim 1 , wherein the first slit is narrower than the second slit. 
     
     
       3. The semiconductor device of  claim 1 , wherein the second slit has a width greater than a width of the vertical structure. 
     
     
       4. The semiconductor device of  claim 1 , wherein the slit insulating layer is formed on a top surface of the first gate stack structure. 
     
     
       5. The semiconductor device of  claim 1 , wherein each of the second channel structures is narrower than each of the first channel structures. 
     
     
       6. The semiconductor device of  claim 1 , wherein the vertical structure includes an insulating material. 
     
     
       7. The semiconductor device of  claim 1 , wherein the vertical structure includes a vertical conductive pattern and an insulating layer extending along a sidewall of the vertical conductive pattern. 
     
     
       8. The semiconductor device of  claim 1 , further comprising:
 a separation insulating layer filling the first slit. 
 
     
     
       9. The semiconductor device of  claim 1 , wherein the second electrode pattern comprises a conductive layer and a liner layer on each of a top surface and a bottom surface of the conductive layer, and
 wherein the liner layer is cut by the first slit overlapping the first gate stack structure.