Key exchange schemes with addressable elements

Abstract

A computing device includes an array of addressable elements. Each addressable element is a hardware element that generates a substantially consistent response when interrogated. The device includes a processor coupled to the array of addressable elements and configured to communicate using a communication network. The processor receives a public key, and processes the public key to produce at least a set of addresses. Each address in the set of addresses identifies one or more hardware elements in the array of addressable elements. The processor generates a set of responses by interrogating the one or more hardware elements in the array of addressable elements identified by the set of addresses according to a set of reading instructions, appends the responses in the set of responses to generate a private key, receives an encrypted message and decrypts the encrypted message using the private key to generate an unencrypted message.

What is claimed is: 
     
       1. A computing device comprising:
 a memory; 
 an array of addressable elements, wherein each addressable element is an element in a cryptographic table having a value; 
 a processor coupled to the array of addressable elements and configured to communicate using a communication network, the processor being configured to execute instructions for:
 receiving, using the network interface, a public key; 
 processing the public key to produce at least a set of addresses, wherein each address in the set of addresses identifies one or more elements in the array of addressable elements; 
 generating a set of responses by reading the value of the elements in the array of addressable elements identified by the set of addresses according to a set of reading instructions; 
 appending the responses in the set of responses to generate a private key; 
 receiving, using the network interface, an encrypted message, and; 
 decrypting the encrypted message using the private key to generate an unencrypted message. 
 
 
     
     
       2. The computing device of  claim 1 , wherein each addressable element is an element in a cryptographic table having a trinary value. 
     
     
       3. The computing device of  claim 1 , wherein processing the public key to produce at least a set of addresses includes:
 combining the public key with an additional identifying information to generate a first input; 
 executing a hash function on the first input to generate a hash digest; and 
 subdividing the hash digest into at least first a set of addresses. 
 
     
     
       4. The computing device of  claim 1 , wherein generating a set of responses further includes a preliminary step comprising:
 generating a preliminary set of responses by interrogating the elements in the array of addressable elements identified by the set of addresses; 
 referencing the preliminary set of responses to a table of modified reading instructions; and 
 incorporating the modified reading instructions into the set of reading instructions. 
 
     
     
       5. The computing device of  claim 4 , wherein each addressable element is an element in a cryptographic table having a trinary value. 
     
     
       6. The computing device of  claim 5 , wherein each trinary element of the cryptographic table holds a value analogous to “0”, “1”, or X″, wherein an element holding a value analogous to “X” denotes that the response from the element holding the value analogous to “X” is to be removed from the set of responses by the set of reading instructions.