Scanning circuit, display panel and display device

Abstract

A scanning circuit, a display panel and a display device. The scanning circuit includes a scanning signal output module, a light emitting control signal output module, a first output control module, a second output control module, a reset module, a clock signal input terminal, a first potential signal input terminal, a second potential signal input terminal, a scanning signal output terminal, a light emitting control signal output terminal, a shift signal input terminal and a reset control signal input terminal.

What is claimed is: 
     
       1. A scanning circuit, comprising a scanning signal output module, a light emitting control signal output module, a first output control module, a second output control module, a reset module, a clock signal input terminal, a first potential signal input terminal, a second potential signal input terminal, a scanning signal output terminal, a light emitting control signal output terminal, a shift signal input terminal and a reset control signal input terminal;
 the first output control module is electrically connected to the shift signal input terminal, the first potential signal input terminal, a first node and a second node, and is configured to control a potential of the first node according to a signal input from the shift signal input terminal, a signal input from the first potential signal input terminal and a potential of the second node; 
 the second output control module is electrically connected to the first potential signal input terminal, the second potential signal input terminal, the first node and a third node, and is configured to control a potential of the third node according to the signal input from the first potential signal input terminal, a signal input from the second potential signal input terminal and the potential of the first node; 
 the reset module is electrically connected to the reset control signal input terminal, the first potential signal input terminal, the first node and the scanning signal output terminal, and is configured to control the potential of the first node according to a signal input from the reset control signal input terminal and the signal input from the first potential signal input terminal, and to reset a signal output from the scanning signal output terminal according to the signal input from the reset control signal input terminal; 
 the scanning signal output module is electrically connected to the clock signal input terminal, the first potential signal input terminal, the first node, the second node and the scanning signal output terminal, and is configured to transmit a signal input from the clock signal input terminal to the scanning signal output terminal according to the potential of the first node, or transmit the signal input from the first potential signal input terminal to the scanning signal output terminal according to the potential of the second node; and 
 the light emitting control signal output module is electrically connected to the first node, the second node, the third node, the first potential signal input terminal and the second potential signal input terminal, the second node is electrically connected to the light emitting control signal output terminal, and the light emitting control signal output module is configured to transmit the signal input from the first potential signal input terminal to the second node according to the potential of the first node, or transmit the signal input from the second potential signal input terminal to the second node according to the potential of the third node, wherein: 
 the second output control module comprises a third transistor and a fourth transistor, a gate and a first pole of the third transistor is electrically connected to the second potential signal input terminal, and a second pole of the third transistor is electrically connected to the third node; 
 a gate of the fourth transistor is electrically connected to the first node, a first pole of the fourth transistor is electrically connected to the first potential signal input terminal, and a second pole of the fourth transistor is electrically connected to the third node; and 
 a channel width of the third transistor is less than a channel width of the fourth transistor. 
 
     
     
       2. The scanning circuit of  claim 1 , wherein the scanning signal output module comprises a first scanning output unit and a second scanning output unit, the first node is configured to control an on state of the first scanning output unit; and the second node is configured to control an on state of the second scanning output unit;
 the first scanning output unit is electrically connected to the clock signal input terminal, the first node and the scanning signal output terminal, and is configured to transmit the signal input from the clock signal input terminal to the scanning signal output terminal when the first scanning output unit is on; and 
 the second scanning output unit is electrically connected to the first potential signal input terminal, the second node and the scanning signal output terminal, and is configured to transmit the signal input from the first potential signal input terminal to the scanning signal output terminal when the second scanning output unit is on. 
 
     
     
       3. The scanning circuit of  claim 2 , wherein the light emitting control signal output module comprises a first light emitting output unit and a second light emitting output unit, the first node is further configured to control an on state of the first light emitting output unit; and the third node is configured to control an on state of the second light emitting output unit;
 the first light emitting output unit is electrically connected to the first node, the first potential signal input terminal and the second node, and is configured to transmit the signal input from the first potential signal input terminal to the second node when the first light emitting output unit is on; 
 the second light emitting output unit is electrically connected to the third node, the second potential signal input terminal and the second node, and is configured to transmit the signal input from the second potential signal input terminal to the second node when the second light emitting output unit is on. 
 
     
     
       4. The scanning circuit of  claim 3 , wherein the reset module comprises a first reset unit and a second reset unit;
 the first reset unit is electrically connected to the reset control signal input terminal, the first potential signal input terminal and the first node, and is configured to transmit the signal input from the first potential signal input terminal to the first node when the first reset unit is on; and 
 the second reset unit is electrically connected to the reset control signal input terminal, the first potential signal input terminal and the scanning signal output terminal, and is configured to transmit the signal input from the first potential signal input terminal to the scanning signal output terminal when the second reset unit is on. 
 
     
     
       5. The scanning circuit of  claim 1 , wherein the first output control module comprises a first transistor and a second transistor, a gate and a first pole of the first transistor is electrically connected to the shift signal input terminal, and a second pole of the first transistor is electrically connected to the first node; and
 a gate of the second transistor is electrically connected to the second node, a first pole of the second transistor is electrically connected to the first potential signal input terminal, and a second pole of the second transistor is electrically connected to the first node. 
 
     
     
       6. The scanning circuit of  claim 2 , wherein the first scanning output unit comprises a fifth transistor and a first capacitor, a first terminal of the first capacitor is electrically connected to a gate of the fifth transistor, and a second terminal of the first capacitor is electrically connected to a first pole of the fifth transistor; the gate of the fifth transistor is electrically connected to the first node, the first pole of the fifth transistor is electrically connected to the clock signal input terminal, and a second pole of the fifth transistor is electrically connected to the scanning signal output terminal. 
     
     
       7. The scanning circuit of  claim 2 , wherein the second scanning signal output unit comprises a sixth transistor; a gate of the sixth transistor is electrically connected to the second node, a first pole of the sixth transistor is electrically connected to the first potential signal input terminal, and a second pole of the sixth transistor is electrically connected to the scanning signal output terminal. 
     
     
       8. The scanning circuit of  claim 3 , wherein the first light emitting output unit comprises a seventh transistor, a gate of the seventh transistor is electrically connected to the first node, a first pole of the seventh transistor is electrically connected to the first potential signal input terminal, and a second pole of the seventh transistor is electrically connected to the second node. 
     
     
       9. The scanning circuit of  claim 3 , wherein the second light emitting output unit comprises an eighth transistor; a gate of the eighth transistor is electrically connected to the third node, a first pole of the eighth transistor is electrically connected to the second potential signal input terminal, and a second pole of the eighth transistor is electrically connected to the second node. 
     
     
       10. The scanning circuit of  claim 4 , wherein the first reset unit comprises a ninth transistor; a gate of the ninth transistor is electrically connected to the reset control signal input terminal, a first pole of the ninth transistor is electrically connected to the first potential signal input terminal, and a second pole of the ninth transistor is electrically connected to the first node. 
     
     
       11. The scanning circuit of  claim 4 , wherein the second reset unit comprises a tenth transistor, a gate of the tenth transistor is electrically connected to the reset control signal input terminal, a first pole of the tenth transistor is electrically connected to the first potential signal input terminal, and a second pole of the tenth transistor is electrically connected to the scanning signal output terminal. 
     
     
       12. The scanning circuit of  claim 5 , wherein each of the first transistor and the second transistor is a P-type transistor or an N-type transistor. 
     
     
       13. A display panel, comprising: at least two scanning circuits of  claim 1 , a first clock signal line, a second clock signal line, a first potential signal line, a second potential signal line and a start signal line;
 in each of the at least two scanning circuits, the first potential signal input terminal is electrically connected to the first potential signal line, and the second potential signal input terminal is electrically connected to the second potential signal line; 
 the at least two scanning circuits are connected in cascade, and the shift signal input terminal of a first-stage scanning circuit of the at least two scanning circuits is electrically connected to the start signal line; in two adjacent stages of the at least two scanning circuits, the scanning signal output terminal of a previous-stage scanning circuit is electrically connected to the shift signal input terminal of a subsequent-stage scanning circuit; 
 in the two adjacent stages of the at least two scanning circuits, the clock signal input terminal of the previous-stage scanning circuit is electrically connected to the first clock signal line, and the clock signal input terminal of the subsequent-stage scanning circuit is electrically connected to the second clock signal line; and 
 the reset control signal input terminal of the previous-stage scanning circuit is electrically connected to the scanning signal output terminal of the subsequent-stage scanning circuit. 
 
     
     
       14. The display panel of  claim 13 , wherein a clock signal supplied by the first clock signal line is opposite to a clock signal supplied by the second clock signal line. 
     
     
       15. The display panel of  claim 13 , further comprising: a cut-off signal line, wherein in a case where the subsequent-stage scanning circuit is a last-stage scanning circuit, the reset control signal input terminal of the last-stage scanning circuit is connected to the cut-off signal line, and the cut-off signal line is configured to supply a reset control signal for the last-stage scanning circuit. 
     
     
       16. The display panel of  claim 13 , wherein the display panel is an organic light emitting diode display panel, a liquid crystal display panel or an electronic paper display panel. 
     
     
       17. A display device, comprising: the display panel of  claim 13 . 
     
     
       18. The scanning circuit of  claim 1 , wherein a charging time and a discharging time are different between the fourth transistor and the third transistor. 
     
     
       19. The scanning circuit of  claim 18 , wherein when both the third transistor and the fourth transistor are on, the third node maintains a potential input from the first potential signal input terminal by at least one predetermined factor, and the at least one predetermined factor includes the difference of the discharging time and the charging time between the third transistor and the fourth transistor. 
     
     
       20. The scanning circuit of  claim 6 , wherein the first terminal of the first capacitor is further electrically connected to the first node so that a potential of the first node is stored by the first capacitor and maintained for a predetermined period, wherein due to a bootstrapping effect of the first capacitor, the potential of the first node changes from vgl−Vth to 2×vgl−Vth−vgh, wherein vgl is the signal input from the second potential signal input terminal, Vth is a threshold voltage of a first transistor, and vgh is the signal input from the first potential signal input terminal.