Selectively writing back dirty cache lines concurrently with processing

Abstract

A graphics pipeline includes a cache having cache lines that are configured to store data used to process frames in a graphics pipeline. The graphics pipeline is implemented using a processor that processes frames for the graphics pipeline using data stored in the cache. The processor processes a first frame and writes back a dirty cache line from the cache to a memory concurrently with processing of the first frame. The dirty cache line is retained in the cache and marked as clean subsequent to being written back to the memory. In some cases, the processor generates a hint that indicates a priority for writing back the dirty cache line based on a read command occupancy at a system memory controller.

What is claimed is: 
     
       1. An apparatus comprising:
 a cache comprising cache lines that are configured to store data used to process frames in a graphics pipeline; and 
 a processor implementing the graphics pipeline, wherein the processor is configured to process a first frame and selectively write back a dirty cache line from the cache to a memory based on a read command occupancy at a system memory controller (SMC) and concurrently with processing of the first frame, wherein data in the dirty cache line is retained in the cache and marked as clean subsequent to being written back to the memory. 
 
     
     
       2. The apparatus of  claim 1 , wherein the processor is configured to transmit data in the dirty cache line to the SMC in response to the read command occupancy being less than a first threshold, wherein the SMC is configured to write the data received from the processor back to the memory. 
     
     
       3. The apparatus of  claim 2 , wherein the processor is configured to transmit the data in the dirty cache line to the SMC with a hint that indicates that writing the data back to the memory is a low priority in response to the read command occupancy being greater than the first threshold and less than a second threshold. 
     
     
       4. The apparatus of  claim 3 , wherein the SMC is configured to serve pending read requests before writing the data back to the memory in response to receiving the hint. 
     
     
       5. The apparatus of  claim 4 , wherein the processor is configured to bypass transmitting the data in the dirty cache line to the SMC in response to the read command occupancy being greater than the second threshold. 
     
     
       6. The apparatus of  claim 1 , wherein the processor is configured to bypass writing the dirty cache line back to the memory during a transition from the first frame to a second frame in response to the dirty cache line being marked as clean. 
     
     
       7. The apparatus of  claim 6 , wherein the processor is configured to write back data in dirty cache lines that are not marked as clean in response to completing processing of the first frame and initiating processing of a second frame. 
     
     
       8. A method comprising:
 processing, in a graphics pipeline, a first frame using data stored in cache lines of a cache associated with the graphics pipeline; 
 selectively writing a dirty cache line from the cache back to a memory based on a read command occupancy at a system memory controller (SMC); 
 retaining the data in the dirty cache line in the cache; and 
 marking the dirty cache line as clean subsequent to the dirty cache line being written back to the memory. 
 
     
     
       9. The method of  claim 8 , wherein writing back the dirty cache line comprises transmitting data in the dirty cache line to the SMC in response to the read command occupancy being less than a first threshold. 
     
     
       10. The method of  claim 9 , further comprising:
 writing the data received from the SMC back to the memory. 
 
     
     
       11. The method of  claim 9 , wherein writing back the dirty cache line comprises transmitting the data in the dirty cache line to the SMC with a hint that indicates that writing the data back to the memory is a low priority in response to the read command occupancy being greater than the first threshold and less than a second threshold. 
     
     
       12. The method of  claim 11 , further comprising:
 serving, at the SMC, pending read requests before writing the data back to the memory in response to receiving the hint. 
 
     
     
       13. The method of  claim 12 , wherein selectively writing the dirty cache line back to the memory comprises bypassing transmission of the data in the dirty cache line to the SMC in response to the read command occupancy being greater than the second threshold. 
     
     
       14. The method of  claim 8 , further comprising:
 bypassing writing the dirty cache line back to the memory during a transition from the first frame to a second frame in response to the dirty cache line being marked as clean. 
 
     
     
       15. The method of  claim 14 , further comprising:
 writing back data in dirty cache lines that are not marked as clean in response to completing processing of the first frame and initiating processing of a second frame. 
 
     
     
       16. An apparatus comprising:
 a set of compute units configured to implement a graphics pipeline; and 
 a last level cache (LLC) in a cache hierarchy associated with the compute units, wherein the compute units are configured to selectively write back dirty cache lines from the LLC to a memory based on a read command occupancy for a system memory controller (SMC) and concurrently with processing a first frame based on data stored in the dirty cache lines, and wherein the dirty cache lines are marked as clean subsequent to being written back to the memory. 
 
     
     
       17. The apparatus of  claim 16 , wherein the compute units are configured to determine priorities for writing back the dirty cache lines from the LLC to the memory based on the read command occupancy for the SMC. 
     
     
       18. The apparatus of  claim 16 , wherein the compute units are configured to bypass writing a dirty cache line back to the memory during a transition from the first frame to a second frame in response to the dirty cache line being marked as clean, and wherein the compute units are configured to write back data in dirty cache lines that are not marked as clean in response to completing processing of the first frame and initiating processing of a second frame.