Layout structure for shared analog bus in unit element multiplier

Abstract

A planar fabrication charge transfer capacitor for coupling charge from a Unit Element (UE) generates a positive charge first output V_PP and a positive charge second output V_NP, the first output coupled to a positive charge line comprising a continuous first planar conductor, a continuous second planar conductor parallel to the first planar conductor, and a continuous third planar conductor parallel to the first planar conductor and second planar conductor, the charge transfer capacitor comprising, in sequence: a first co-planar conductor segment, the first planar conductor, a second co-planar conductor segment, the second planar conductor, a third co-planar conductor segment, the third planar conductor, and a fourth coplanar conductor segment, the first and third coplanar conductor segments capacitively edge coupled to the UE first output V_PP, the second and fourth coplanar conductor segments capacitively edge coupled to the UE second output V_NP.

We claim: 
     
       1. A charge transfer capacitor coupling charge from a positive multiplier-accumulator (MAC) Unit Element (UE) and a negative MAC UE to a positive charge transfer line and a negative charge transfer line, the positive UE generating complementary outputs V_PP and V_PN, the negative UE generating complementary outputs V_NN and V_NP, the charge transfer capacitor comprising:
 a continuous first conductor, a continuous second conductor parallel and co-planar to the first conductor, and a continuous third conductor parallel and co-planar to the second conductor, the continuous first conductor, continuous second conductor, and continuous third conductor coupled to the positive charge transfer line; 
 a first conductor segment adjacent to the continuous first conductor and co-planar to the continuous first conductor, the first conductor segment coupled to V_PP; 
 a second conductor segment adjacent to the continuous first conductor and also adjacent to the continuous second conductor and co-planar to the continuous first conductor and the continuous second conductor, the second conductor segment coupled to V_NP; 
 a third conductor segment adjacent to the continuous second conductor and also adjacent to the continuous third conductor, and co-planar to the continuous second conductor and the continuous second conductor, the third conductor segment coupled to V_PP; 
 a fourth conductor segment adjacent to the continuous third conductor, and co-planar to the continuous third conductor, the fourth conductor segment coupled to V_NP. 
 
     
     
       2. The charge transfer capacitor of  claim 1  where the continuous first conductor, continuous second conductor, and continuous third conductor are connected to each other by conductors on a layer which is not co-planar to the continuous first conductor. 
     
     
       3. The charge transfer capacitor of  claim 1  where the first conductor segment, third conductor segment, and V_PP are connected together by a conductor which is not co-planar to the second conductor segment. 
     
     
       4. The charge transfer capacitor of  claim 1  where the second conductor segment, fourth conductor segment, and V_NP are connected together by a conductor which is not co-planar to the second conductor segment. 
     
     
       5. The charge transfer capacitor of  claim 1  where V_PP and V_NP are outputs from at least one of NAND gate or an inverter gate. 
     
     
       6. A charge transfer capacitor comprising:
 a first conductor, second conductor, and third conductor parallel to each other and electrically connected to each other; 
 a first conductor segment having an edge capacitively coupled to an edge of the first conductor; 
 a second conductor segment having a first edge capacitively coupled to an opposite edge of the first conductor and a second edge capacitively coupled to an edge of the second conductor; 
 a third conductor segment having a first edge capacitively coupled to an opposite edge of the second conductor and also a second edge capacitively coupled to an edge of the third conductor; 
 a fourth conductor segment having an edge capacitively coupled to an opposite edge of the third conductor; 
 the first conductor segment and third conductor segment electrically coupled together and to a first input voltage from a multiplier-accumulator (MAC) unit element; 
 the second conductor segment and fourth conductor segment electrically coupled together and to a second input voltage from the MAC unit element. 
 
     
     
       7. The charge transfer capacitor of  claim 6  where the first conductor, second conductor, third conductor, first conductor segment, second conductor segment, third conductor segment, and fourth conductor segment are co-planar. 
     
     
       8. The charge transfer capacitor of  claim 6  where the first conductor, second conductor, and third conductor are connected to each other by a trace which is on a different planar surface than the first conductor, second conductor, and third conductor. 
     
     
       9. The charge transfer capacitor of  claim 6  where the first conductor segment, second conductor segment, third conductor segment, and fourth conductor segment are in the same extent with each other over a long axis extent segment of the first conductor. 
     
     
       10. A charge transfer capacitor for a positive multiplier-accumulator (MAC) unit element generating a positive output and a negative output and a negative MAC unit element generating a positive output and a negative output, the charge transfer capacitor comprising:
 a first positive conductor, a second positive conductor, and a third positive conductor; 
 a first positive conductor segment having an edge capacitively coupled to an edge of the first positive conductor, a second positive conductor segment having an edge capacitively coupled to an edge of the first positive conductor and also capacitively coupled to an edge of the second positive conductor, a third positive conductor segment having an edge capacitively coupled to an edge of the second positive conductor and also having an edge capacitively coupled to an edge of the third positive conductor, and a fourth positive conductor segment having an edge capacitively coupled to an edge of the third positive conductor segment; 
 a first negative conductor, a second negative conductor, and a third negative conductor; 
 a first negative conductor segment having an edge capacitively coupled to an edge of the first negative conductor, a second negative conductor segment having an edge capacitively coupled to an edge of the first negative conductor and also having an edge capacitively coupled to an edge of the second negative conductor, a third negative conductor segment having an edge capacitively coupled to an edge of the second negative conductor and also having an edge capacitively coupled to an edge of the third negative conductor, and a fourth negative conductor segment having an edge capacitively coupled to an edge of the third negative conductor; 
 the positive unit element positive output coupled to the first positive conductor segment and the third positive conductor segment; 
 the negative unit element positive output coupled to the second positive conductor segment and the fourth positive conductor segment; 
 the positive unit element negative output coupled to the first negative conductor segment and the third negative conductor segment; 
 the negative unit element negative output coupled to the second negative conductor segment and the fourth negative conductor segment. 
 
     
     
       11. The charge transfer capacitor of  claim 10  where the first positive conductor, the second positive conductor, and the third positive conductor are co-planar and periodically interconnected by a conductive layer positioned an insulating layer below a layer of the first positive conductor. 
     
     
       12. The charge transfer capacitor of  claim 10  where the first negative conductor, the second negative conductor, and the third negative conductor are co-planar and periodically interconnected by a conductive layer positioned an insulating layer below a co-planar layer of the first negative conductor. 
     
     
       13. The charge transfer capacitor of  claim 10  where the first positive conductor segment, the second positive conductor segment, and the third positive conductor segment are co-planar with, and interleaved with, the first positive conductor, second positive conductor, and third positive conductor. 
     
     
       14. The charge transfer capacitor of  claim 10  where the first negative conductor segment, the second negative conductor segment, and the third negative conductor segment are co-planar with, and interleaved with, the first negative conductor, second negative conductor, and third negative conductor. 
     
     
       15. The charge transfer capacitor of  claim 10  where a gap from an edge of at least one of the first positive conductor segment, second positive conductor segment, and third positive conductor segment to an edge of at least one of the first positive conductor, the second positive conductor, and third positive conductor is substantially equal to a gap from an edge of a different one of the first positive conductor segment, second positive conductor segment, and third positive conductor segment to an edge of at least one of the first positive conductor, the second positive conductor, and third positive conductor. 
     
     
       16. The charge transfer capacitor of  claim 10  where the first positive conductor segment, the second positive conductor segment, the third positive conductor segment, the first negative conductor segment, the second negative conductor segment, and the third negative conductor segment are parallel to each other and located in a common extent of the first positive conductor or the first negative conductor. 
     
     
       17. A charge transfer capacitor for a positive signal voltage from a multiplier-accumulator (MAC) unit element and a complementary negative signal voltage from the MAC unit element, the charge transfer capacitor comprising:
 a plurality of elongate positive conductors periodically connected to each other over an elongate extent; 
 a plurality of elongate negative conductors periodically connected to each other over an elongate extent; 
 a plurality of positive conductor segments coupled to the positive signal voltage, the plurality of positive conductor segments co-planar to the plurality of elongate positive conductors and positioned between the plurality of elongate positive conductors, the plurality of positive conductor segments capacitively edge capacitively coupled to the plurality of elongate positive conductors; 
 a plurality of negative conductor segments coupled to the complementary negative signal voltage, the plurality of negative conductor segments co-planar to the plurality of elongate negative conductors and positioned between the plurality of elongate negative conductors, the plurality of negative conductor segments capacitively edge coupled to the plurality of elongate negative conductors; 
 whereby a transition of the positive signal voltage and complementary transition of the negative signal voltage causes an opposite but substantially equal charge displacement to the elongate positive conductor and elongate negative conductor. 
 
     
     
       18. The charge transfer capacitor of  claim 17  where the elongate positive conductors and the positive conductor segments are on a first layer, and a second layer different than the first layer has interconnections between the elongate positive conductors and interconnections between the positive conductor segments. 
     
     
       19. The charge transfer capacitor of  claim 17  where the positive signal is driven by a NAND gate output and the negative complementary signal is driven by the output of an inverter having an input coupled to the NAND gate output.