Shared command shifter systems and methods

Abstract

The systems and methods described herein involve a device that may receive a plurality of commands and generate a common command indicative of matching data signals between each of the plurality of commands. The device may include a first latch that receives a shifted flag and outputs a shifted command in response to a first enable signal. The device may include shifters, where a first shifter may receive the common command, and a last shifter may couple to the first latch. The last shifter may receive a shifter common command and may generate the first enable signal using the shifted common command.

What is claimed is: 
     
       1. A device, comprising:
 an input stage configured to receive a plurality of commands and to generate a common command indicative of matching data signals between each of the plurality of commands; 
 a first latch configured to receive a shifted flag and to output a shifted command in response to a first enable signal; and 
 a command shifter comprising a plurality of shifters, wherein a first shifter of the plurality of shifters is configured to couple to the input stage to receive the common command, wherein a second shifter of the plurality of shifters is configured to couple to the first latch, and wherein the second shifter receives the common command from the first shifter and generates the first enable signal using the common command. 
 
     
     
       2. The device of  claim 1 , comprising:
 a third shifter disposed between the first shifter and the second shifter, wherein the third shifter is configured to generate a second enable signal in response to receiving the common command and to transmit the second enable signal to a second latch. 
 
     
     
       3. The device of  claim 2 , wherein the second latch is coupled to the third shifter, and wherein the second latch is configured to receive a decoded flag and to output the decoded flag in response to the second enable signal. 
     
     
       4. The device of  claim 3 , comprising a decoder configured to generate four decoded flags based at least in part on two command flags corresponding to the plurality of commands, wherein the four decoded flags comprise the decoded flag, and wherein values of each of the two command flags comprise values for each of the plurality of commands over time. 
     
     
       5. The device of  claim 1 , wherein the input stage comprises a sampling circuitry configured to identify the matching data signals between each of the plurality of commands based at least in part on identifying which address bits are shared by each of the plurality of commands. 
     
     
       6. The device of  claim 5 , wherein the sampling circuitry is configured to output the address bits as the common command. 
     
     
       7. The device of  claim 6 , wherein any remaining address bits of the plurality of commands are configured to be transmitted via a flag decoder configured to recapture the plurality of commands based on the remaining address bits in response to the common command being output from the second shifter. 
     
     
       8. The device of  claim 1 , wherein the input stage comprises an OR logic gate. 
     
     
       9. The device of  claim 1 , wherein a pair of address stages transmit a burst chop address during a partially overlapping time period with transmission of the common command. 
     
     
       10. The device of  claim 1 , wherein the plurality of commands comprises a read command, a read non-target command, a write command, a write non-target command, or any combination thereof. 
     
     
       11. A method of operating a memory device, comprising:
 receiving, via an input stage of a circuit, a first memory command; 
 generating, via the input stage, a common command comprising a portion of the first memory command that matches a portion of a second memory command also received at the input stage; 
 shifting, via a command shifter of the circuit, the common command; 
 transmitting, via the command shifter, a first enable signal to a storage and processing stage of a flag decoder configured to transmit a decoded flag corresponding to the first memory command, wherein the first enable signal is generated in response to the common command being shifted through a respective shifter of the command shifter; and 
 transmitting, via the command shifter, a second enable signal to a clock gate of the flag decoder, wherein the clock gate is configured to receive a shifted command flag from the storage and processing stage, wherein the clock gate is configured to transmit a first command in response to the second enable signal to align timing of the first command with an edge of the second enable signal, and wherein the first command is transmitted in association with the shifted command. 
 
     
     
       12. The method of  claim 11 , comprising generating, via the command shifter, the second enable signal as the common command. 
     
     
       13. The method of  claim 11 , comprising:
 transmitting, via the command shifter, the first enable signal to a plurality of storage and processing stages of the flag decoder, wherein the plurality of storage and processing stages comprises the storage and processing stage. 
 
     
     
       14. The method of  claim 13 , wherein the plurality of storage and processing stages are configured to transmit respective decoded flags including the decoded flag at different times corresponding to rising edges of the common command. 
     
     
       15. The method of  claim 14 , wherein the respective decoded flags each comprise a combination of logic signals indicative of memory command types comprising a read command type, a read non-target command type, a write command type, and a write non-target command type. 
     
     
       16. A system, comprising:
 a command decoder configured to receive instructions from processing circuitry of a host device and generate a plurality of memory commands based on the instructions; 
 shifting circuitry coupled to the command decoder, wherein the shifting circuitry is configured to receive the plurality of memory commands from the command decoder and transmit the plurality of memory commands after shifting the plurality of memory commands, wherein to transmit the plurality of memory commands, the shifting circuitry is configured to:
 receive the plurality of memory commands; 
 transmit a data signal comprising signals common to each of the plurality of memory commands as a common command via a command shifter; 
 transmit a data signal comprising signals different between a subset of the plurality of memory commands via a flag decoder; and 
 capture the plurality of memory commands from an output from the command shifter and an output from the flag decoder as a plurality of shifted memory commands; and 
 
 memory bank control circuitry configured to receive the plurality of shifted memory commands. 
 
     
     
       17. The system of  claim 16 , wherein the shifting circuitry is configured to compensate for a transmission delay during transmission of the plurality of memory commands through the command shifter via a walkback operation. 
     
     
       18. The system of  claim 16 , wherein the data signal common to each of the plurality of memory commands is generated in response to a logic gate toggling an output based on respective active levels of each of the plurality of memory commands. 
     
     
       19. The system of  claim 16 , wherein the shifting circuitry comprises:
 an input stage configured to receive the plurality of memory commands and to generate the common command; 
 a first latch configured to receive a shifted flag corresponding to the data signal and to output a shifted command of the plurality of shifted memory commands in response to a first enable signal; and 
 wherein the command shifter comprises a plurality of shifters, wherein a first shifter of the plurality of shifters is coupled to the input stage to receive the common command, wherein a last shifter of the plurality of shifters is coupled to the first latch, and wherein the last shifter receives the common command from the first shifter and generates the first enable signal using the common command. 
 
     
     
       20. The system of  claim 16 , wherein the memory bank control circuitry is configured to write or read data from a memory bank responsive to the plurality of shifted memory commands.