Phase shifter with bidirectional amplification

Abstract

An apparatus is disclosed for bidirectional amplification with phase-shifting. In example implementations, an apparatus includes a phase shifter with a bidirectional amplifier. The bidirectional amplifier includes a first transistor coupled between a first plus node and a second minus node, a second transistor coupled between a first minus node and a second plus node, a third transistor coupled between the first plus node and the second minus node, and a fourth transistor coupled between the first minus node and the second plus node. The bidirectional amplifier also includes a fifth transistor coupled between the first plus node and the second plus node, a sixth transistor coupled between the first minus node and the second minus node, a seventh transistor coupled between the first plus node and the second plus node, and an eighth transistor coupled between the first minus node and the second minus node.

What is claimed is: 
     
       1. An apparatus comprising:
 a phase shifter comprising:
 a first differential interface comprising a first plus node and a first minus node; 
 a second differential interface comprising a second plus node and a second minus node; and 
 a bidirectional amplifier comprising:
 a first transistor bank comprising:
 a first transistor coupled between the first plus node and the second minus node; 
 a second transistor coupled between the first minus node and the second plus node; 
 a third transistor coupled between the first plus node and the second minus node; 
 a fourth transistor coupled between the first minus node and the second plus node; 
 a fifth transistor coupled between the first plus node and the second plus node; 
 a sixth transistor coupled between the first minus node and the second minus node; 
 a seventh transistor coupled between the first plus node and the second plus node; and 
 an eighth transistor coupled between the first minus node and the second minus node; and 
 
 a second transistor bank comprising:
 a ninth transistor coupled between the second plus node and the first plus node; 
 a tenth transistor coupled between the second minus node and the first minus node; 
 an eleventh transistor coupled between the second plus node and the first plus node; 
 a twelfth transistor coupled between the second minus node and the first minus node; 
 a thirteenth transistor coupled between the second plus node and the first minus node; 
 a fourteenth transistor coupled between the second minus node and the first plus node; 
 a fifteenth transistor coupled between the second plus node and the first minus node; and 
 a sixteenth transistor coupled between the second minus node and the first plus node, wherein: 
 
 
 the first differential interface comprises an input of the first transistor bank and an output of the second transistor bank; and 
 the second differential interface comprises an output of the first transistor bank and an input of the second transistor bank. 
 
 
     
     
       2. The apparatus of  claim 1 , wherein the bidirectional amplifier is configured to:
 amplify a signal that is flowing from the first differential interface to the second differential interface using the first transistor bank; and 
 amplify another signal that is flowing from the second differential interface to the first differential interface using the second transistor bank. 
 
     
     
       3. The apparatus of  claim 1 , wherein:
 the first, second, third, fourth, fifth, sixth, seventh, and eighth transistors each approximately have a first size; 
 the ninth, tenth, eleventh, twelfth, thirteenth, fourteenth, fifteenth, and sixteenth transistors each approximately have a second size; and 
 the first size is substantially different from the second size. 
 
     
     
       4. The apparatus of  claim 3 , wherein the first size and the second size correspond to at least one of channel width, channel length, or effective channel width. 
     
     
       5. The apparatus of  claim 1 , wherein:
 with regard to the first, second, third, fourth, fifth, sixth, seventh, and eighth transistors:
 the first plus node and the first minus node comprise a first differential signaling input of the bidirectional amplifier with respect to a first signal propagation direction corresponding to the first transistor bank; and 
 the second plus node and the second minus node comprise a first differential signaling output of the bidirectional amplifier with respect to the first signal propagation direction; and 
 
 with regard to the ninth, tenth, eleventh, twelfth, thirteenth, fourteenth, fifteenth, and sixteenth transistors:
 the second plus node and the second minus node comprise a second differential signaling input of the bidirectional amplifier with respect to a second signal propagation direction corresponding to the second transistor bank; and 
 the first plus node and the first minus node comprise a second differential signaling output of the bidirectional amplifier with respect to the second signal propagation direction. 
 
 
     
     
       6. The apparatus of  claim 1 , wherein the phase shifter is configured to propagate an in-phase signal component (I signal component) through the bidirectional amplifier and between the first differential interface and the second differential interface. 
     
     
       7. The apparatus of  claim 1 , wherein:
 a gate terminal of the first transistor is coupled to the first plus node, and a drain terminal of the first transistor is coupled to the second minus node; 
 a gate terminal of the second transistor is coupled to the first minus node, and a drain terminal of the second transistor is coupled to the second plus node; 
 a gate terminal of the third transistor is coupled to the first plus node, and a drain terminal of the third transistor is coupled to the second minus node; 
 a gate terminal of the fourth transistor is coupled to the first minus node, and a drain terminal of the fourth transistor is coupled to the second plus node; 
 a gate terminal of the fifth transistor is coupled to the first plus node, and a drain terminal of the fifth transistor is coupled to the second plus node; 
 a gate terminal of the sixth transistor is coupled to the first minus node, and a drain terminal of the sixth transistor is coupled to the second minus node; 
 a gate terminal of the seventh transistor is coupled to the first plus node, and a drain terminal of the seventh transistor is coupled to the second plus node; and 
 a gate terminal of the eighth transistor is coupled to the first minus node, and a drain terminal of the eighth transistor is coupled to the second minus node. 
 
     
     
       8. The apparatus of  claim 7 , wherein the bidirectional amplifier further comprises:
 first plus bias voltage circuitry coupled to the gate terminal of the first transistor, the gate terminal of the third transistor, the gate terminal of the fifth transistor, and the gate terminal of the seventh transistor; and 
 first minus bias voltage circuitry coupled to the gate terminal of the second transistor, the gate terminal of the fourth transistor, the gate terminal of the sixth transistor, and the gate terminal of the eighth transistor. 
 
     
     
       9. The apparatus of  claim 7 , wherein:
 the first plus node and the first minus node comprise a differential signaling input of the bidirectional amplifier with respect to the first transistor bank; and 
 the second plus node and the second minus node comprise a differential signaling output of the bidirectional amplifier with respect to the first transistor bank. 
 
     
     
       10. The apparatus of  claim 1 , wherein the bidirectional amplifier further comprises:
 a first plus capacitor coupled between the first plus node and the first, third, fifth, and seventh transistors; and 
 a first minus capacitor coupled between the first minus node and the second, fourth, sixth, and eighth transistors. 
 
     
     
       11. The apparatus of  claim 10 , further comprising:
 at least one power distribution network (PDN) node (PDN node), wherein: 
 the first, third, sixth, and eighth transistors are direct-current-coupled (DC-coupled) to the at least one PDN node via the second minus node; and 
 the second, fourth, fifth, and seventh transistors are DC-coupled to the at least one PDN node via the second plus node. 
 
     
     
       12. The apparatus of  claim 1 , wherein the bidirectional amplifier further comprises:
 a first enablement device coupled between:
 the first transistor and at least one power distribution network (PDN) node (PDN node); and 
 the second transistor and the at least one PDN node; 
 
 a second enablement device coupled between:
 the third transistor and the at least one PDN node; and 
 the fourth transistor and the at least one PDN node; 
 
 a third enablement device coupled between:
 the fifth transistor and the at least one PDN node; and 
 the sixth transistor and the at least one PDN node; and 
 
 a fourth enablement device coupled between:
 the seventh transistor and the at least one PDN node; and 
 the eighth transistor and the at least one PDN node. 
 
 
     
     
       13. The apparatus of  claim 12 , wherein:
 the first enablement device is configured to enable a first direct-current (DC) current to flow through or to disable the first DC current from flowing through the first transistor and the second transistor; 
 the second enablement device is configured to enable a second DC current to flow through or to disable the second DC current from flowing through the third transistor and the fourth transistor; 
 the third enablement device is configured to enable a third DC current to flow through or to disable the third DC current from flowing through the fifth transistor and the sixth transistor; and 
 the fourth enablement device is configured to enable a fourth DC current to flow through or to disable the fourth DC current from flowing through the seventh transistor and the eighth transistor. 
 
     
     
       14. The apparatus of  claim 13 , wherein:
 the first enablement device comprises a first enablement transistor; 
 the second enablement device comprises a second enablement transistor; 
 the third enablement device comprises a third enablement transistor; and 
 the fourth enablement device comprises a fourth enablement transistor. 
 
     
     
       15. The apparatus of  claim 12 , wherein:
 the at least one PDN node comprises a ground node; and 
 each of the first, second, third, fourth, fifth, sixth, seventh, and eighth transistors comprises a respective n-channel metal-oxide-semiconductor (MOS) field-effect transistor (FET) (nMOSFET). 
 
     
     
       16. The apparatus of  claim 12 , wherein:
 the at least one PDN node comprises at least one power supply node; and 
 each of the first, second, third, fourth, fifth, sixth, seventh, and eighth transistors comprises a respective p-channel metal-oxide-semiconductor (MOS) field-effect transistor (FET) (pMOSFET). 
 
     
     
       17. The apparatus of  claim 12 , wherein the bidirectional amplifier is configured to be in an active mode or an inactive mode based on at least one of the first, second, third, or fourth enablement device enabling at least one direct-current (DC) current to flow. 
     
     
       18. The apparatus of  claim 17 , wherein:
 the active mode comprises a first active mode; and 
 the bidirectional amplifier is configured to be in the first active mode based on the first enablement device and the second enablement device jointly enabling the at least one DC current to flow through the first, second, third, and fourth transistors. 
 
     
     
       19. The apparatus of  claim 18 , wherein:
 the active mode comprises the first active mode and a second active mode; and 
 the bidirectional amplifier is configured to be in the second active mode based on the third enablement device and the fourth enablement device jointly enabling the at least one DC current to flow through the fifth, sixth, seventh, and eighth transistors. 
 
     
     
       20. The apparatus of  claim 19 , wherein the bidirectional amplifier is configured to output a differential signal having a polarity that is inverted responsive to operating in the second active mode relative to operating in the first active mode. 
     
     
       21. The apparatus of  claim 18 , wherein the bidirectional amplifier is configured to be in the first active mode based on the third enablement device and the fourth enablement device jointly disabling the at least one DC current from flowing through the fifth, sixth, seventh, and eighth transistors. 
     
     
       22. The apparatus of  claim 17 , wherein the bidirectional amplifier is configured to be in the inactive mode based on the second enablement device and the third enablement device jointly enabling the at least one DC current to flow through the third, fourth, fifth, and sixth transistors. 
     
     
       23. The apparatus of  claim 22 , wherein the bidirectional amplifier is configured to be in the inactive mode based on the first enablement device and the fourth enablement device jointly disabling the at least one DC current from flowing through the first, second, seventh, and eighth transistors. 
     
     
       24. The apparatus of  claim 17 , wherein:
 the bidirectional amplifier is configured to be in the inactive mode based on two enablement devices of the first, second, third, or fourth enablement devices jointly enabling the at least one DC current to flow through four transistors of the first, second, third, fourth, fifth, sixth, seventh, and eighth transistors; each of the four transistors coupled to at least one of the two enablement devices; 
 two of the four transistors are coupled to the second plus node and the second minus node with a first polarity; and 
 another two of the four transistors are coupled to the second plus node and the second minus node with a second polarity, the second polarity different from the first polarity. 
 
     
     
       25. The apparatus of  claim 1 , wherein:
 the bidirectional amplifier comprises a first bidirectional amplifier that corresponds to a first amplification amount; and 
 the phase shifter comprises a variable gain amplifier (VGA), the VGA comprising the first bidirectional amplifier and a second bidirectional amplifier that corresponds to a second amplification amount, the second amplification amount different from the first amplification amount. 
 
     
     
       26. The apparatus of  claim 25 , wherein transistors of the first bidirectional amplifier and transistors of the second bidirectional amplifier have different weighting factors to cause the first amplification amount and the second amplification amount to be different. 
     
     
       27. The apparatus of  claim 26 , wherein the transistors of the first bidirectional amplifier have different sizes than the transistors of the second bidirectional amplifier. 
     
     
       28. The apparatus of  claim 25 , wherein the phase shifter comprises:
 a signal phase generator; and 
 a vector modulator coupled to the signal phase generator, the vector modulator comprising the VGA. 
 
     
     
       29. The apparatus of  claim 28 , wherein the signal phase generator is configured to generate a first signal component having a first phase and a second signal component having a second phase, the first phase and the second phase separated by 90 degrees (90°). 
     
     
       30. The apparatus of  claim 28 , wherein:
 the VGA comprises a first VGA associated with a first phase of a signal; 
 the vector modulator comprises a second VGA associated with a second phase of the signal; 
 the first VGA is coupled to the signal phase generator via a first transformer; and 
 the second VGA is coupled to the signal phase generator via a second transformer. 
 
     
     
       31. The apparatus of  claim 28 , further comprising:
 a signal coupler; 
 a power amplifier; and 
 a low-noise amplifier, 
 wherein the phase shifter is coupled switchably between:
 the signal coupler and the power amplifier; or 
 the signal coupler and the low-noise amplifier. 
 
 
     
     
       32. The apparatus of  claim 1 , further comprising:
 an antenna array comprising multiple antenna elements, at least one antenna element of the multiple antenna elements coupled to the phase shifter; and 
 a wireless interface device coupled to the antenna array, the wireless interface device comprising the phase shifter and configured to steer wireless signals communicated via the antenna array using the bidirectional amplifier of the phase shifter. 
 
     
     
       33. The apparatus of  claim 32 , further comprising:
 a display screen; and 
 a processor operatively coupled to the display screen and the wireless interface device, the processor configured to present one or more graphical images on the display screen based on the wireless signals steered by the wireless interface device using the bidirectional amplifier of the phase shifter. 
 
     
     
       34. An apparatus comprising:
 a phase shifter comprising:
 a first plus node; 
 a first minus node; 
 a second plus node; 
 a second minus node; and 
 a bidirectional amplifier comprising:
 a first transistor coupled between the first plus node and the second minus node; 
 a second transistor coupled between the first minus node and the second plus node; 
 a third transistor coupled between the first plus node and the second minus node; 
 a fourth transistor coupled between the first minus node and the second plus node; 
 a fifth transistor coupled between the first plus node and the second plus node; 
 a sixth transistor coupled between the first minus node and the second minus node; 
 a seventh transistor coupled between the first plus node and the second plus node; and 
 an eighth transistor coupled between the first minus node and the second minus node, 
 a gate terminal of the first transistor coupled to the first plus node, and a drain terminal of the first transistor coupled to the second minus node; 
 a gate terminal of the second transistor coupled to the first minus node, and a drain terminal of the second transistor coupled to the second plus node; 
 a gate terminal of the third transistor coupled to the first plus node, and a drain terminal of the third transistor coupled to the second minus node; 
 a gate terminal of the fourth transistor coupled to the first minus node, and a drain terminal of the fourth transistor coupled to the second plus node; 
 a gate terminal of the fifth transistor coupled to the first plus node, and a drain terminal of the fifth transistor coupled to the second plus node; 
 a gate terminal of the sixth transistor coupled to the first minus node, and a drain terminal of the sixth transistor coupled to the second minus node; 
 a gate terminal of the seventh transistor coupled to the first plus node, and a drain terminal of the seventh transistor coupled to the second plus node; and 
 a gate terminal of the eighth transistor coupled to the first minus node, and a drain terminal of the eighth transistor coupled to the second minus node. 
 
 
 
     
     
       35. The apparatus of  claim 34 , wherein the bidirectional amplifier further comprises:
 first plus bias voltage circuitry coupled to the gate terminal of the first transistor, the gate terminal of the third transistor, the gate terminal of the fifth transistor, and the gate terminal of the seventh transistor; and 
 first minus bias voltage circuitry coupled to the gate terminal of the second transistor, the gate terminal of the fourth transistor, the gate terminal of the sixth transistor, and the gate terminal of the eighth transistor. 
 
     
     
       36. The apparatus of  claim 34 , wherein:
 the first plus node and the first minus node comprise a differential signaling input of the bidirectional amplifier; and 
 the second plus node and the second minus node comprise a differential signaling output of the bidirectional amplifier. 
 
     
     
       37. An apparatus comprising:
 a phase shifter comprising:
 a first plus node; 
 a first minus node; 
 a second plus node; 
 a second minus node; and 
 a bidirectional amplifier comprising:
 a first transistor coupled between the first plus node and the second minus node; 
 a second transistor coupled between the first minus node and the second plus node; 
 a third transistor coupled between the first plus node and the second minus node; 
 a fourth transistor coupled between the first minus node and the second plus node; 
 a fifth transistor coupled between the first plus node and the second plus node; 
 a sixth transistor coupled between the first minus node and the second minus node; 
 a seventh transistor coupled between the first plus node and the second plus node; 
 an eighth transistor coupled between the first minus node and the second minus node; 
 a first enablement device coupled between:
 the first transistor and at least one power distribution network (PDN) node (PDN node); and 
 the second transistor and the at least one PDN node; 
 
 a second enablement device coupled between:
 the third transistor and the at least one PDN node; and 
 the fourth transistor and the at least one PDN node; 
 
 a third enablement device coupled between:
 the fifth transistor and the at least one PDN node; and 
 the sixth transistor and the at least one PDN node; and 
 
 a fourth enablement device coupled between:
 the seventh transistor and the at least one PDN node; and 
 the eighth transistor and the at least one PDN node. 
 
 
 
 
     
     
       38. The apparatus of  claim 37 , wherein:
 the first enablement device is configured to enable a first direct-current (DC) current to flow through or to disable the first DC current from flowing through the first transistor and the second transistor; 
 the second enablement device is configured to enable a second DC current to flow through or to disable the second DC current from flowing through the third transistor and the fourth transistor; 
 the third enablement device is configured to enable a third DC current to flow through or to disable the third DC current from flowing through the fifth transistor and the sixth transistor; and 
 the fourth enablement device is configured to enable a fourth DC current to flow through or to disable the fourth DC current from flowing through the seventh transistor and the eighth transistor. 
 
     
     
       39. The apparatus of  claim 37 , wherein:
 the at least one PDN node comprises a ground node; and 
 each of the first, second, third, fourth, fifth, sixth, seventh, and eighth transistors comprises a respective n-channel metal-oxide-semiconductor (MOS) field-effect transistor (FET) (nMOSFET). 
 
     
     
       40. The apparatus of  claim 37 , wherein:
 the at least one PDN node comprises at least one power supply node; and 
 each of the first, second, third, fourth, fifth, sixth, seventh, and eighth transistors comprises a respective p-channel metal-oxide-semiconductor (MOS) field-effect transistor (FET) (pMOSFET). 
 
     
     
       41. The apparatus of  claim 37 , wherein the bidirectional amplifier is configured to be in an active mode or an inactive mode based on at least one of the first, second, third, or fourth enablement device enabling at least one direct-current (DC) current to flow. 
     
     
       42. The apparatus of  claim 41 , wherein:
 the active mode comprises a first active mode and a second active mode; 
 the bidirectional amplifier is configured to be in the first active mode based on the first enablement device and the second enablement device jointly enabling the at least one DC current to flow through the first, second, third, and fourth transistors; and 
 the bidirectional amplifier is configured to be in the second active mode based on the third enablement device and the fourth enablement device jointly enabling the at least one DC current to flow through the fifth, sixth, seventh, and eighth transistors. 
 
     
     
       43. The apparatus of  claim 42 , wherein the bidirectional amplifier is configured to output a differential signal having a polarity that is inverted responsive to operating in the second active mode relative to operating in the first active mode. 
     
     
       44. The apparatus of  claim 42 , wherein the bidirectional amplifier is configured to be in the first active mode based on the third enablement device and the fourth enablement device jointly disabling the at least one DC current from flowing through the fifth, sixth, seventh, and eighth transistors. 
     
     
       45. The apparatus of  claim 41 , wherein the bidirectional amplifier is configured to be in the inactive mode based on the second enablement device and the third enablement device jointly enabling the at least one DC current to flow through the third, fourth, fifth, and sixth transistors. 
     
     
       46. The apparatus of  claim 45 , wherein the bidirectional amplifier is configured to be in the inactive mode based on the first enablement device and the fourth enablement device jointly disabling the at least one DC current from flowing through the first, second, seventh, and eighth transistors. 
     
     
       47. The apparatus of  claim 41 , wherein:
 the bidirectional amplifier is configured to be in the inactive mode based on two enablement devices of the first, second, third, or fourth enablement devices jointly enabling the at least one DC current to flow through four transistors of the first, second, third, fourth, fifth, sixth, seventh, and eighth transistors; each of the four transistors coupled to at least one of the two enablement devices; 
 two of the four transistors are coupled to the second plus node and the second minus node with a first polarity; and 
 another two of the four transistors are coupled to the second plus node and the second minus node with a second polarity, the second polarity different from the first polarity.