Dual mode digital filters for RF sampling transceivers

Abstract

Dual mode filters having two reconfigurable multi-stage filters. In a dual band mode, each reconfigurable filter filters an input signal in a different band using every filter stage. In a single band mode, both reconfigurable filters are effectively divided into two sub-chains that include either the odd-numbered filter stages or the even-numbered filter stages. Together, the four sub-chains in the single band mode filter an input signal in a single band with a higher parallelization than each reconfigurable filter in the dual band mode. In some embodiments, the dual mode filter is a decimation filter. In other embodiments, the dual mode filter is a resampling filter. In still other embodiments, the dual mode filter is an interpolation filter.

What is claimed is: 
     
       1. A dual mode filter having a higher parallelization mode and a lower parallelization mode, the dual mode filter comprising:
 a first reconfigurable filter and a second reconfigurable filter, each reconfigurable filter comprising a plurality of filter stages, the plurality of filter stages including a penultimate filter stage and a final filter stage, each filter stage comprising:
 a multiplexer configured to select either a partial sum generated by a filter stage immediately preceding the filter stage or a partial sum generated by a filter stage immediately preceding the immediately preceding filter stage; 
 one or more multipliers, each coupled to an input signal and one of a plurality of unique filter coefficients and having an output operable to output a filtered input signal; and 
 an adder coupled to at least one multiplier and operable to generate a partial sum for the filter stage by adding the one or more filtered input signals and the partial sum selected by the multiplexer. 
 
 
     
     
       2. The dual mode filter of  claim 1 , wherein the dual mode filter is a decimation filter or a resampling filter. 
     
     
       3. The dual mode filter of  claim 1 , wherein, in the lower parallelization mode, each multiplexer in each filter stage is configured to select the partial sum generated by the immediately preceding filter stage. 
     
     
       4. The dual mode filter of  claim 3 , further comprising:
 a mode-based processor that, in the lower parallelization mode, outputs the partial sums generated by the adders in the final filter stage of each of the reconfigurable filters. 
 
     
     
       5. The dual mode filter of  claim 3 , wherein, in the lower parallelization mode:
 the first reconfigurable filter generates a filtered output of a first input signal in a first band; and 
 the second reconfigurable filter generates a filtered output of a second input signal in a second band. 
 
     
     
       6. The dual mode filter of  claim 3 , wherein, in the higher parallelization mode, each multiplexer in each filter stage is configured to select the partial sum generated by the filter stage immediately preceding the immediately preceding filter stage. 
     
     
       7. The dual mode filter of  claim 6 , wherein:
 each reconfigurable filter includes a set of odd-numbered filter stages alternating with a set of even-numbered filter stages; and 
 in the higher parallelization mode, the adder in the final filter stage of each reconfigurable filter generates a partial sum filtered by the even-numbered filter stages and the adder in the penultimate filter stage of each reconfigurable filter generates a partial sum filtered by the odd-numbered filter stages. 
 
     
     
       8. The dual mode filter of  claim 6 , further comprising:
 a mode-based processor that, in the higher parallelization mode:
 generates a first filtered output by adding the partial sum generated by the adder in the final filter stage of the first reconfigurable filter and the partial sum generated by the adder in the penultimate filter stage of the second reconfigurable filter; and 
 generates a second filtered output by adding the partial sum generated by the adder in the final filter stage of the second reconfigurable filter and the partial sum generated by the adder in the penultimate filter stage of the first reconfigurable filter. 
 
 
     
     
       9. The dual mode filter of  claim 6 , wherein, in the higher parallelization mode, both of the reconfigurable filters filter an input signal in the same band. 
     
     
       10. The dual mode filter of  claim 1 , wherein each reconfigurable filter further comprises an initial filter stage, the initial filter stage comprising an initial stage multiplier, coupled to the input signal and one of the plurality of unique filter coefficients, operable to generate a partial sum for the initial filter stage by filtering the input signal. 
     
     
       11. The dual mode filter of  claim 1 , wherein each reconfigurable filter further comprises an initial filter stage, the initial filter stage comprising:
 a plurality of initial stage multipliers, each coupled to the input signal and one of the plurality of unique filter coefficients and having an output operable to output a filtered input signal; and 
 an initial stage adder coupled to the plurality of initial stage multipliers and operable to generate a partial sum for the initial filter stage by adding the filtered input signals output by the initial stage multipliers. 
 
     
     
       12. The dual mode filter of  claim 1 , wherein each reconfigurable filter further comprises a second filter stage, the second filter stage comprising:
 a plurality of second stage multipliers, each coupled to the input signal and one of the plurality of unique filter coefficients and having an output operable to output a filtered input signal; 
 a second stage multiplexer configured to select and output either a partial sum generated by an initial filter stage or 0; and 
 a second stage adder coupled to the plurality of second stage multipliers and operable to generate a partial sum for the second filter stage by adding the filtered input signals output by the second stage multipliers to the output of the second stage multiplexer. 
 
     
     
       13. The dual mode filter of  claim 12 , wherein:
 in the lower parallelization mode, the second stage multiplexer is configured to select the partial sum generated by the initial filter stage; and 
 in the higher parallelization mode, the second stage multiplexer is configured to select 0. 
 
     
     
       14. A dual mode interpolation filter having a lower parallelization mode and a higher parallelization mode, the dual mode interpolation filter comprising:
 a first reconfigurable filter and a second reconfigurable filter, each reconfigurable filter comprising: 
 a plurality of filter stages, each filter stage comprising:
 a multiplexer configured to select either an input sample provided by a filter stage immediately preceding the filter stage or an input sample provided by a filter stage immediately preceding the immediately preceding filter stage; and 
 one or more multipliers that each filter the input signal selected by the multiplexer; and 
 
 adders coupled to the multipliers configured to generate output samples by summing the outputs of the multipliers. 
 
     
     
       15. The dual mode interpolation filter of  claim 14 , wherein, in the lower parallelization mode, each multiplexer in each filter stage is configured to select the partial sum generated by the immediately preceding filter stage. 
     
     
       16. The dual mode interpolation filter of  claim 15 , further comprising:
 a mode-based processor that, in the lower parallelization mode:
 provides a first input signal in a first band to the first reconfigurable filter; and 
 provides a second input signal in a second band to the second reconfigurable filter. 
 
 
     
     
       17. The dual mode interpolation filter of  claim 14 , wherein, in the higher parallelization mode, each multiplexer in each filter stage is configured to select the partial sum generated by the filter stage immediately preceding the immediately preceding filter stage. 
     
     
       18. The dual mode interpolation filter of  claim 17 , further comprising:
 a mode-based processor that, in the higher parallelization mode, is configured to provide input samples in the same band to both the first reconfigurable filter and the second reconfigurable filter. 
 
     
     
       19. A transceiver, comprising:
 one or more dual mode filters, each dual mode filter comprising a first reconfigurable filter and a second reconfigurable filter, each reconfigurable filter comprising a plurality of filter stages, each filter stage comprising: 
 a multiplexer configured to select either a partial sum generated by a filter stage immediately preceding the filter stage or a partial sum generated by a filter stage immediately preceding the immediately preceding filter stage; 
 one or more multipliers, each coupled to an input signal and one of a plurality of unique filter coefficients and having an output operable to output a filtered input signal; and 
 an adder coupled to at least one multiplier and operable to generate a partial sum for the filter stage by adding the one or more filtered input signals and the partial sum selected by the multiplexer. 
 
     
     
       20. The transceiver of  claim 19 , wherein the one or more dual mode filters comprise a dual mode resampling filter or a dual mode decimation filter. 
     
     
       21. The transceiver of  claim 20 , comprising:
 a digital up-converter comprising a dual mode interpolation filter; and 
 a digital down-converter, comprising: 
 the dual mode resampling filter; and 
 the dual mode decimation filter.