Storage array invalidation maintenance

Abstract

Techniques are disclosed relating to managing storage array invalidations. A computer system may comprise a processor core configured to operate in an idle state and operate in a run state in which the processor core executes instructions. The computer system may further comprise a power management circuit that is configured to receive, while the processor core is in the idle state, a set of invalidation requests directed to the processor core to invalidate a set of entries of a storage array of the processor core. The power management circuit may store invalidation information indicative of the set of invalidation requests. The power management circuit may determine that the processor core has received a request to transition to the run state. Prior to the processor core operating in the run state, the power management circuit may invalidate the set of entries of the storage array based on the invalidation information.

What is claimed is: 
     
       1. A system, comprising:
 a processor core configured to:
 operate in an idle state in which the processor core does not execute instructions but is not in a powered-off state; and 
 operate in a run state in which the processor core executes instructions; 
 
 a cache circuit configured to send, to the processor core, invalidation requests directed to the processor core; and 
 a power management circuit coupled to the processor core and the cache circuit, wherein the power management circuit includes an invalidation buffer and is configured to:
 transition the processor core from the run state to the idle state; 
 communicate with the cache circuit to block invalidation requests associated with a storage array of the processor core from reaching the processor core; 
 receive, from the cache circuit and while the processor core is in the idle state, a set of notifications about a first set of invalidation requests directed to the processor core to invalidate a set of entries of the storage array of the processor core; 
 store, in the invalidation buffer, first invalidation information that is indicative of the first set of invalidation requests; 
 based on a detection of a request to transition the processor core to the run state from the idle state, invalidate the set of entries of the storage array based on the first invalidation information; and 
 based on a detection of a request to transition the processor core to the powered-off state from the idle state, discard the first invalidation information. 
 
 
     
     
       2. The system of  claim 1 , further comprising:
 an invalidation counter, wherein the power management circuit is configured to increment a value of the invalidation counter in response to receiving a notification about an invalidation request directed to the processor core. 
 
     
     
       3. The system of  claim 2 , wherein the power management circuit is configured to:
 determine that an overflow has occurred in the invalidation counter; and 
 in response to determining that the overflow has occurred, invalidate all entries of the storage array prior to the processor core operating in the run state. 
 
     
     
       4. The system of  claim 2 , wherein the power management circuit is configured to:
 detect that the processor core is to transition to the idle state; and 
 reset the value of the invalidation counter in response to detecting that the processor core is to transition to the idle state. 
 
     
     
       5. The system of  claim 1 , wherein the first invalidation information specifies a set of memory addresses, and wherein the set of entries correspond to those entries of the storage array that store data for respective ones of the set of memory addresses. 
     
     
       6. The system of  claim 1 , wherein the power management circuit is configured to:
 receive, while the processor core is in the idle state, another set of notifications about a second set of invalidation requests directed to the processor core to invalidate a set of entries of a translation lookaside buffer (TLB) of the processor core; 
 store second invalidation information indicative of the second set of invalidation requests; and 
 prior to the processor core operating in the run state, invalidate the set of entries of the TLB based on the second invalidation information. 
 
     
     
       7. The system of  claim 1 , wherein the storage array is an instruction cache configured to store one or more instructions that are retrievable by the processor core for execution. 
     
     
       8. The system of  claim 1 , wherein the power management circuit comprises:
 a power state machine configured to transition the processor core from the run state to the idle state. 
 
     
     
       9. The system of  claim 1 , wherein to discard the first invalidation information, the power management circuit is configured to:
 reset a value of an invalidation counter used to track a number of invalidation requests that is received while the processor core is in the idle state; and 
 invalidate entries of the invalidation buffer that store a set of memory addresses identified by the first set of invalidation requests. 
 
     
     
       10. A non-transitory computer readable medium having stored thereon design information that specifies a circuit design in a format recognized by a fabrication system that is configured to use the design information to fabricate a hardware integrated circuit that comprises:
 a power management circuit that includes a first invalidation buffer and is configured to:
 transition a first processor core to an idle state in which the first processor core does not execute instructions but is not in a powered-off state; 
 communicate with a cache circuit to block invalidation requests associated with a storage array of the first processor core from reaching the first processor core; 
 receive, from the cache circuit and while the first processor core is in the idle state, a set of notifications about a first set of invalidation requests directed to the first processor core to invalidate a set of entries of the storage array of the first processor core; 
 store, in the first invalidation buffer, first invalidation information that is indicative of the first set of invalidation requests; 
 based on a detection of a request to transition the first processor core from the idle state to a run state in which the first processor core executes instructions, invalidate the set of entries of the storage array based on the first invalidation information; and 
 based on a detection of a request to transition the first processor core from the idle state to the powered-off state, discard the first invalidation information. 
 
 
     
     
       11. The medium of  claim 10 , wherein the power management circuit is configured to:
 receive, while the first processor core is in the idle state, another set of notifications about a second set of invalidation requests directed to the first processor core to invalidate a set of entries of a cache of the first processor core; 
 store second invalidation information indicative of the second set of invalidation requests; and 
 prior to the first processor core being in the run state, invalidate the set of entries of the cache based on the second invalidation information. 
 
     
     
       12. The medium of  claim 11 , wherein the power management circuit includes:
 a second, separate invalidation buffer, wherein the power management circuit is configured to store the second invalidation information in the second invalidation buffer. 
 
     
     
       13. The medium of  claim 11 , wherein the power management circuit is configured to store the first and second invalidation information in the first invalidation buffer, wherein the first invalidation information specifies a first set of memory addresses and the second invalidation information specifies a second set of memory addresses, and wherein the first invalidation buffer stores indications that the first set of memory addresses is associated with the storage array and the second set of memory addresses is associated with the cache. 
     
     
       14. The medium of  claim 10 , wherein the power management circuit is configured to:
 track a number of notifications of invalidation requests received at the power management circuit; and 
 in response to the number of notifications satisfying a threshold value, invalidate all entries of the storage array prior to the first processor core operating in the run state. 
 
     
     
       15. The medium of  claim 10 , wherein the storage array is a first translation lookaside buffer (TLB), and wherein the hardware integrated circuit further comprises:
 a second processor core coupled to the first processor core, wherein the second processor core is configured to:
 modify data stored in an entry of a second TLB of the second processor core; and 
 in response to modifying the data, issue an invalidation request directed to the first processor core to invalidate an entry of the first TLB that stores the data. 
 
 
     
     
       16. The medium of  claim 10 , wherein the power management circuit is configured to:
 after invalidating the set of entries of the storage array, transition the first processor core to the run state. 
 
     
     
       17. The medium of  claim 10 , wherein the power management circuit includes an override circuit that is configured to cause, in response to a debug value being set, the power management circuit to invalidate all entries of the storage array prior to the first processor core operating in the run state. 
     
     
       18. A method, comprising:
 transitioning, by a power management circuit of an integrated circuit, a processor core of the integrated circuit to an idle state in which the processor core does not execute instructions but is not in a powered-off state; 
 communicating, by the power management circuit, with a cache circuit of the integrated circuit to block invalidation requests associated with a storage array of the processor core from reaching the processor core; 
 while the processor core is operating in the idle state, the power management circuit:
 receiving, from the cache circuit, a set of notifications about a first set of invalidation requests directed to the processor core to invalidate a first set of entries of the storage array of the processor core; and 
 storing, in an invalidation buffer of the power management circuit, first invalidation information that is indicative of the first set of invalidation requests; 
 
 determining, by the power management circuit, that the processor core has received a request to transition to a run state in which the processor core executes instructions; and 
 prior to the processor core operating in the run state, the power management circuit invalidating the first set of entries of the storage array based on the first invalidation information, wherein the power management circuit is configured to discard the first invalidation information in response to a detection of a request to transition the processor core from the idle state to the powered-off state instead of the run state. 
 
     
     
       19. The method of  claim 18 , further comprising:
 while the processor core is operating in the idle state, the power management circuit:
 receiving another set of notifications about a second set of invalidation requests directed to the processor core to invalidate a set of entries of a translation lookaside buffer (TLB) of the processor core; and 
 storing second invalidation information that is indicative of the second set of invalidation requests; and 
 
 prior to the processor core operating in the run state, the power management circuit invalidating the set of entries of the TLB based on the second invalidation information.