Sensing a memory cell

Abstract

Devices and methods for sensing a memory cell are described. The memory cell may include a ferroelectric memory cell. During a read operation, a first switching component may selectively couple a sense component with the memory cell based on a logic state stored on the memory cell to transfer a charge between the memory cell and the sense component. A second switching component, which may be coupled with the first switching component, may down convert a voltage associated with the charge to another voltage that is within an operation voltage of the sense component. The sense component may operate at a lower voltage than a voltage at which the memory cell operates to reduce power consumption in some cases.

What is claimed is: 
     
       1. A method, comprising:
 precharging a digit line during a read operation; 
 activating a word line to couple a memory cell with the digit line after precharging the digit line; 
 transferring, based at least in part on activating the word line, a charge between the memory cell and a sense component through a circuit configured to reduce a voltage associated with the charge during the read operation; and 
 determining a logic state stored on the memory cell based at least in part on the charge transferred through the circuit. 
 
     
     
       2. The method of  claim 1 , further comprising:
 biasing a gate of a first switching component of the circuit to a second voltage based at least in part on coupling the digit line with a first node. 
 
     
     
       3. The method of  claim 2 , further comprising:
 activating the first switching component to couple the sense component with the first node based at least in part on biasing the gate of the first switching component to the second voltage when the memory cell stores a high logic state. 
 
     
     
       4. The method of  claim 3 , further comprising:
 down converting, by a second switching component of the circuit, the voltage associated with the charge to a third voltage, wherein the third voltage is lower than the voltage associated with the charge by an amount corresponding to a threshold voltage of the second switching component. 
 
     
     
       5. The method of  claim 2 , further comprising:
 maintaining the first switching component in a deactivated state when the gate of the first switching component is biased to the second voltage when the memory cell stores a low logic state. 
 
     
     
       6. The method of  claim 1 , wherein transferring the charge between the memory cell and the sense component through the circuit further comprises:
 activating the circuit to couple the sense component with the memory cell when the memory cell transfers a first charge indicative of a high logic state to a first node during the read operation. 
 
     
     
       7. The method of  claim 6 , further comprising:
 down converting a voltage associated with the first charge for the sense component based at least in part on activating the circuit to couple the sense component with the memory cell. 
 
     
     
       8. The method of  claim 1 , wherein determining the logic state stored on the memory cell further comprises:
 comparing a reduced voltage associated with the charge transferred through the circuit with a reference voltage of the sense component. 
 
     
     
       9. The method of  claim 1 , further comprising:
 precharging a first node to a first voltage based at least in part on precharging the digit line; and 
 isolating the digit line from the first node for a duration during the read operation based at least in part on precharging the first node to the first voltage, wherein activating the word line to couple the memory cell with the digit line is based at least in part on isolating the digit line from the first node. 
 
     
     
       10. The method of  claim 9 , further comprising:
 recoupling the digit line with the first node after the duration during the read operation based at least in part on activating the word line, wherein transferring the charge between the memory cell and the sense component is based at least in part on recoupling the digit line with the first node. 
 
     
     
       11. The method of  claim 1 , further comprising:
 coupling the digit line with a first node that has been precharged to a first voltage based at least in part on activating the word line, wherein transferring the charge between the memory cell and the sense component is based at least in part on coupling the digit line with the first node. 
 
     
     
       12. The method of  claim 11 , wherein coupling the digit line with the first node establishes the voltage at the first node indicative of the logic state stored on the memory cell. 
     
     
       13. The method of  claim 1 , further comprising:
 activating the sense component based at least in part on transferring the charge between the memory cell and the sense component; and 
 establishing a second voltage at a second node associated with the sense component based at least in part on activating the sense component, wherein the second voltage is indicative of the logic state stored on the memory cell. 
 
     
     
       14. An apparatus, comprising:
 a memory array comprising a memory cell coupled with a digit line and a word line; and 
 a controller coupled with the memory array and operable to cause the apparatus to:
 precharge the digit line during a read operation; 
 activate the word line to couple the memory cell with the digit line after precharging the digit line; 
 transfer, based at least in part on activating the word line, a charge between the memory cell and a sense component through a circuit configured to reduce a voltage associated with the charge during the read operation; and 
 determine a logic state stored on the memory cell based at least in part on the charge transferred through the circuit. 
 
 
     
     
       15. The apparatus of  claim 14 , wherein the controller is further operable to cause the apparatus to:
 bias a gate of a first switching component of the circuit to a second voltage based at least in part on coupling the digit line with a first node. 
 
     
     
       16. The apparatus of  claim 15 , wherein the controller is further operable to cause the apparatus to:
 activate the first switching component to couple the sense component with the first node based at least in part on biasing the gate of the first switching component to the second voltage when the memory cell stores a high logic state. 
 
     
     
       17. The apparatus of  claim 16 , wherein the controller is further operable to cause the apparatus to:
 down convert, by a second switching component of the circuit, the voltage associated with the charge to a third voltage, wherein the third voltage is lower than the voltage associated with the charge by an amount corresponding to a threshold voltage of the second switching component. 
 
     
     
       18. The apparatus of  claim 15 , wherein the controller is further operable to cause the apparatus to:
 maintain the first switching component in a deactivated state when the gate of the first switching component is biased to the second voltage when the memory cell stores a low logic state. 
 
     
     
       19. The apparatus of  claim 14 , wherein, to transfer the charge between the memory cell and the sense component through the circuit, the controller is further operable to cause the apparatus to:
 activate the circuit to couple the sense component with the memory cell when the memory cell transfers a first charge indicative of a high logic state to a first node during the read operation. 
 
     
     
       20. An apparatus, comprising:
 a digit line configured to be precharged during a read operation; 
 a word line configured to be activated to couple a memory cell with the digit line after precharging the digit line; and 
 a circuit configured to transfer, based at least in part on activating the word line, a charge between the memory cell and a sense component, the circuit further configured to reduce a voltage associated with the charge during the read operation, wherein the sense component is configured to determine a logic state stored on the memory cell based at least in part on the charge transferred through the circuit.