Systems and methods for runtime analog sanitization of memory

Abstract

A system performs analog memory sanitization by forcing voltage levels in memory cells to substantially the same voltage level so that they are indistinguishable regardless of the data that has been previously stored in the cells. In some embodiments, a special programming operation for sanitizing a plurality of memory cells forces the charge in the cells to approximately the same voltage level by increasing the voltage level of all cells regardless of the data currently stored in the cells. As an example, each cell may be programmed to a logical high bit value (e.g., a “0”) by increasing the charge in each cell to a voltage level that is greater than the voltage level for writing the same logical bit value in a normal programming operation. Thus, after the programming operation is performed, the voltage levels of cells storing one logical bit value (e.g., a “0”) prior to the programming operation may be indistinguishable from voltage levels of cells storing a different logical bit value (e.g., a “1”) prior to the programming operation.

Now, therefore, the following is claimed: 
     
       1. A memory system, comprising:
 memory having a plurality of memory cells; and 
 circuitry for reading from and writing to the plurality of memory cells, the circuitry configured to program at least one of the plurality of memory cells to a logical bit value in a first programming operation for writing data to the plurality of memory cells by successively applying a first plurality of pulses to the at least one memory cell until an analog voltage level of the at least one memory cell exceeds a first reference voltage corresponding with the logical bit value such that the at least one memory cell indicates the logical bit value when the analog voltage level exceeds the first reference voltage, the circuitry further configured to program each of the plurality of memory cells to the logical bit value in a second programming operation for sanitizing the plurality of memory cells by successively applying a second plurality of pulses to each of the memory cells until an analog voltage level of the respective memory cell exceeds a second reference voltage that is greater than the first reference voltage. 
 
     
     
       2. The memory system of  claim 1 , wherein the circuitry is configured to apply the first plurality of pulses to a control gate of the at least one memory cell, and wherein circuitry is configured to apply the first reference voltage to the control gate for reading the at least one memory cell between successive pulses of the first plurality of pulses. 
     
     
       3. The memory system of  claim 2 , wherein the circuitry is configured to apply the second plurality of pulses to the control gate, and wherein circuitry is configured to apply the second reference voltage to the control gate for reading the at least one memory cell between successive pulses of the second plurality of pulses. 
     
     
       4. A memory system, comprising:
 memory having at least one memory cell; and 
 circuitry for reading from and writing to the memory cell, the circuitry configured to program the memory cell to a logical bit value in a first programming operation by successively applying a first plurality of pulses to a control gate of the memory cell until an analog voltage level of the at least one memory cell exceeds a first reference voltage corresponding with the logical bit value such that the at least one memory cell indicates the logical bit value when the analog voltage level exceeds the first reference voltage, wherein each of the first plurality of pulses causes charge to flow to a floating gate of the memory cell thereby increasing the analog voltage level of the memory cell, the circuitry configured to perform the first programming operation by applying the first reference voltage for reading the memory cell between successive pulses of the first plurality of pulses, the circuitry configured to program the memory cell to the logical bit value in a second programming operation for sanitizing at least a portion of the memory by successively applying a second plurality of pulses to the control gate of the memory cell until the analog voltage level of the at least one memory cell exceeds a second reference voltage, wherein each of the second plurality of pulses causes charge to flow to the floating gate of the memory cell thereby increasing the analog voltage level of the memory cell, the circuitry configured to perform the second programming operation by applying the second reference voltage for reading the memory cell between successive pulses of the second plurality of pulses, wherein the second reference voltage is greater than the first reference voltage. 
 
     
     
       5. A method for use in a memory system, comprising:
 programming at least one of a plurality of memory cells of the memory system to a logical bit value in a first programming operation for writing data to the plurality of memory cells; 
 applying, to a control gate of at least one of the plurality of memory cells, a first reference voltage corresponding with the logical bit value such that the at least one of the plurality of memory cells indicates the logical bit value when an analog voltage level of the at least one of the plurality of memory cells exceeds the first reference voltage, wherein the programming in the first programming operation comprises successively applying a first plurality of pulses to the control gate until the analog voltage level of the at least one of the plurality of memory cells exceeds the first reference voltage; 
 programming each of the plurality of memory cells to the logical bit value in a second programming operation for sanitizing the plurality of memory cells; and 
 applying a second reference voltage to the control gate, wherein the programming in the second programming operation comprises successively applying a second plurality of pulses to the control gate until the analog voltage level of the at least one of the plurality of memory cells exceeds the second reference voltage, and wherein the second reference voltage is greater than the first reference voltage. 
 
     
     
       6. The method of  claim 5 , wherein the applying the first reference voltage comprises applying the first reference voltage to the control gate for reading the at least one of the plurality of memory cells between successive pulses of the first plurality of pulses. 
     
     
       7. The method of  claim 6 , wherein the applying the second reference voltage comprises applying the second reference voltage to the control gate for reading the at least one of the plurality of memory cells between successive pulses of the second plurality of pulses.