Power-on reset (POR) circuit

Abstract

Embodiments of power-on reset (POR) circuits are described. In one embodiment, a POR circuit includes a primary ladder circuit connected to a supply voltage and configured to generate a reference signal for a reset signal in response to the supply voltage and a secondary ladder circuit connected to the supply voltage and configured to bias the primary ladder circuit in response to the supply voltage.

What is claimed is: 
     
       1. A power-on reset (POR) circuit, the POR circuit comprising:
 a primary ladder circuit coupled to a supply voltage and configured to generate a reference signal for a reset signal in response to the supply voltage; 
 a secondary ladder circuit coupled to the supply voltage and configured to bias the primary ladder circuit in response to the supply voltage; 
 a reference circuit coupled to the supply voltage; and 
 a comparator coupled to the supply voltage; 
 wherein the comparator is configured to compare an output voltage of the secondary ladder circuit with a first voltage in the reference circuit to generate a comparison result signal. 
 
     
     
       2. The POR circuit of  claim 1 ,
 wherein the secondary ladder circuit is configured to bias the primary ladder circuit as a current source when the supply voltage is higher than a voltage threshold. 
 
     
     
       3. The POR circuit of  claim 1 ,
 wherein the secondary ladder circuit is configured to bias the primary ladder circuit as a switch when the supply voltage is lower than a voltage threshold. 
 
     
     
       4. The POR circuit of  claim 1 ,
 wherein the primary ladder circuit comprises a first transistor coupled to the supply voltage and a plurality of diode-connected transistors coupled to the first transistor. 
 
     
     
       5. The POR circuit of  claim 4 ,
 wherein the secondary ladder circuit is configured to bias the first transistor of the primary ladder circuit as a current source when the supply voltage is higher than a voltage threshold. 
 
     
     
       6. The POR circuit of  claim 4 ,
 wherein the secondary ladder circuit is configured to bias the first transistor of the primary ladder circuit as a switch when the supply voltage is lower than a voltage threshold. 
 
     
     
       7. The POR circuit of  claim 4 ,
 wherein the first transistor of the primary ladder circuit comprises a metal-oxide-semiconductor field-effect transistor (MOSFET) transistor or a bipolar junction transistor (BJT). 
 
     
     
       8. The POR circuit of  claim 7 ,
 wherein the diode-connected transistors of the primary ladder circuit comprise a plurality of MOSFET transistors or a plurality of BJTs. 
 
     
     
       9. The POR circuit of  claim 1 ,
 wherein the secondary ladder circuit comprises a plurality of diode-connected transistors. 
 
     
     
       10. The POR circuit of  claim 9 ,
 wherein the diode-connected transistors of the secondary ladder circuit comprise a plurality of metal-oxide-semiconductor field-effect transistor (MOSFET) transistors or a plurality of bipolar junction transistors (BJTs). 
 
     
     
       11. The POR circuit of  claim 1 ,
 further comprising a buffer circuit coupled to the supply voltage and between the comparator and the primary ladder circuit. 
 
     
     
       12. The POR circuit of  claim 11 ,
 wherein the buffer circuit is configured to generate a buffered signal to a transistor of the primary ladder circuit based on the comparison result signal and a second voltage in the reference circuit. 
 
     
     
       13. A power-on reset (POR) circuit, the POR circuit comprising:
 a primary ladder circuit coupled between a first supply voltage and a second supply voltage and configured to generate a reference signal for a reset signal in response to the first supply voltage and the second supply voltage; 
 a secondary ladder circuit coupled between the first supply voltage and the second supply voltage and configured to bias the primary ladder circuit in response to at least one of the first supply voltage and the second supply voltage; 
 a reference circuit coupled to the first and second supply voltages; 
 a comparator coupled to the first and second supply voltages; and 
 a buffer circuit coupled to the first and second supply voltages and between the comparator and the primary ladder circuit. 
 
     
     
       14. A power-on reset (POR) circuit, the POR circuit comprising:
 a primary ladder circuit coupled to a supply voltage and configured to generate a reference signal for a reset signal in response to the supply voltage reaching a first defined voltage trip level; and 
 a secondary ladder circuit coupled to the supply voltage and configured to bias the primary ladder circuit in response to the supply voltage reaching a second defined voltage trip level.