Mux decoder with polarity transition capability

Abstract

A decoder in an integrated circuit memory device having: a positive section having a first input line; a negative section having a second input line; and an output line connected from both the positive section and the negative section to a voltage driver connected to a memory cell. The positive section and the negative section are controlled by a polarity control signal. When the polarity control signal indicates positive polarity, the positive section drives the output line according to signals received in the first input line; and when the polarity control signal indicates negative polarity, the negative section drives the output line according to signals received in the second input line.

What is claimed is: 
     
       1. A device, comprising:
 a voltage driver; 
 a first section having a first input line; 
 a second section having a second input line; 
 an output line connected from the first section and the second section to the voltage driver; and 
 a control line connected to the first section and the second section; 
 wherein when the control line has a first voltage level, the output line is driven by the first section according to signals received in the first input line; and 
 wherein when the control line has a second voltage level, the output line is driven by the second section according to signals received in the second input line. 
 
     
     
       2. The device of  claim 1 , wherein when the control line has the first voltage level, the voltage driver is configured to apply a voltage in a first polarity relative to ground; and when the control line has the second voltage level, the voltage driver is configured to apply a voltage in a second polarity, different from the first polarity, relative to the ground. 
     
     
       3. The device of  claim 1 , further comprising:
 a decoder in an integrated circuit, the decoder comprising the first section, the second section, and the output line. 
 
     
     
       4. The device of  claim 3 , wherein when the control line has the first voltage level, the first section is powered by a positive power voltage relative to ground and disconnected from a negative power voltage relative to the ground. 
     
     
       5. The device of  claim 4 , wherein when the control line has the first voltage level, the first section is connected between the positive power voltage at a first voltage line and the ground at a second voltage line; and the second section is connected between the ground at a third voltage line and the ground at a fourth voltage line. 
     
     
       6. The device of  claim 5 , wherein when the control line has the second voltage level, the first section is connected between the ground at the first voltage line and the ground at the second voltage line; and the second section is connected between the negative power voltage at the third voltage line and the ground at the fourth voltage line. 
     
     
       7. The device of  claim 6 , wherein a gate in the first section is biased at the ground to disconnect the output line from the first voltage line and the second voltage line when the control line is at the second voltage level. 
     
     
       8. The device of  claim 7 , wherein a gate in the second section is biased at a predetermined voltage to disconnect the output line from the third voltage line and the fourth voltage when the control line is at the first voltage level. 
     
     
       9. The device of  claim 8 , wherein when the control line is at the negative power voltage, the second section connects the output line to one of the third voltage line and the fourth voltage line according to a signal received on the second input line. 
     
     
       10. The device of  claim 8 , wherein when the control line is at the positive power voltage, the first section connects the output line to one of the first voltage line and the second voltage line according to a signal received on the first input line. 
     
     
       11. The device of  claim 8 , wherein the decoder has no level shifting circuit. 
     
     
       12. The device of  claim 8 , wherein the decoder performs no pre-charging in operations. 
     
     
       13. A method, comprising:
 applying a first voltage level on a control line connected to a decoder having a first section and a second section; 
 driving, in response to the first voltage level on the control line and by the first section, an output line connected from the first section and the second section to a voltage driver according to signals received in a first input line of the first section; 
 applying a second voltage level on the control line; and 
 driving, in response to the second voltage level on the control line and by the second section, the output line connected to the voltage driver according to signals received in a second input line of the second section. 
 
     
     
       14. The method of  claim 13 , further comprising:
 powering the first section by a first voltage difference between the first voltage level and ground, in response to the control line has the first voltage level; and 
 powering the second section by a second voltage difference between the second voltage level and the ground, in response to the control line has the second voltage level. 
 
     
     
       15. The method of  claim 14 , wherein the first voltage level and the second voltage level are not simultaneously applied to the decoder. 
     
     
       16. The method of  claim 15 , further comprising:
 connecting a gate control line of the first section at the ground, causing when the control line has the second voltage level, the first section to isolate the output line from voltage lines of the first section, wherein the first voltage difference is applied on the voltage lines when the control line has the first voltage level. 
 
     
     
       17. The method of  claim 15 , further comprising:
 connecting a gate control line of the second section at a predetermined voltage, causing when the control line has the first voltage level, the second section to isolate the output line from voltage lines of the second section, wherein the second voltage difference is applied on the voltage lines when the control line has the second voltage level. 
 
     
     
       18. A memory device, comprising:
 a controller; 
 first parallel wires disposed in a first layer; 
 second parallel wires disposed in a second layer; 
 first voltage drivers connected to the first parallel wires respectively; 
 second voltage drivers connected to the second parallel wires respectively; and 
 an array of memory cells formed between the first layer and the second layer, wherein each respective memory cell in the array is at a cross point of a wire in the first layer and a wire in the second layer; 
 wherein each respective voltage driver in the first voltage drivers and the second voltage drivers has a decoder; 
 wherein the decoder comprises:
 a first section having a first input line; 
 a second section having a second input line; 
 an output line connected from the first section and the second section to the respective voltage driver; and 
 a control line connected to the first section and the second section; 
 
 wherein when the control line has a first voltage level, the output line is driven by the first section according to signals received in the first input line; and 
 wherein when the control line has a second voltage level, the output line is driven by the second section according to signals received in the second input line. 
 
     
     
       19. The memory device of  claim 18 , wherein when the control line has the first voltage level, the first section is connected between a positive power voltage at a first voltage line and ground at a second voltage line; and the second section is connected between the ground at a third voltage line and the ground at a fourth voltage line; and
 wherein when the control line has the second voltage level, the first section is connected between the ground at the first voltage line and the ground at the second voltage line; and the second section is connected between a negative power voltage at the third voltage line and the ground at the fourth voltage line. 
 
     
     
       20. The memory device of  claim 19 , wherein when the control line has the second voltage level, the first section is configured to isolate the output line from the first voltage line and the second voltage line; and
 when the control line has the first voltage level, the second section is configured to isolate the output line from the third voltage line and the fourth voltage line.