Electronic component with semiconductor die having a low ohmic portion with an active area and a high ohmic portion on a dielectric layer

Abstract

An electronic component includes a mold layer and a semiconductor die including a low ohmic first portion and a high ohmic second portion. The low ohmic first portion has an active area. The high ohmic second portion is arranged on the mold layer.

What is claimed is: 
     
       1. An electronic component configured to be encapsulated to form a package, the electronic component comprising:
 a mold layer; and 
 a semiconductor die comprising a low ohmic semiconductor portion and a high ohmic semiconductor portion, 
 wherein the low ohmic semiconductor portion has an active area and the high ohmic semiconductor second portion is arranged on the mold layer. 
 
     
     
       2. The electronic component of  claim 1 , wherein the mold layer comprises a mold foil, and/or wherein the mold layer comprises a mold plate. 
     
     
       3. The electronic component of  claim 1 , wherein the mold layer is a double mold layer. 
     
     
       4. The electronic component of  claim 1 , wherein the mold layer comprises a resin matrix and filler particles in the resin matrix, wherein the resin matrix comprises epoxy resin, and wherein the filler particles comprise metal oxide. 
     
     
       5. The electronic component of  claim 1 , wherein the active area has at least one transistor and/or at least one diode. 
     
     
       6. The electronic component of  claim 1 , further comprising an adhesive layer between the mold layer and the semiconductor die. 
     
     
       7. The electronic component of  claim 1 , wherein the active area has a thickness of less than 1 μm. 
     
     
       8. The electronic component of  claim 1 , wherein the semiconductor die has unprocessed semiconductor material with a thickness of less than 150 μm. 
     
     
       9. The electronic component of  claim 1 , wherein the semiconductor die has a thickness in a range from 1 μm to 200 μm. 
     
     
       10. The electronic component of  claim 1 , wherein:
 the high ohmic semiconductor portion comprises a semiconductor material having an electric resistivity of at least 500 Ωcm; and/or 
 the low ohmic semiconductor portion comprises a semiconductor material having an electric resistivity of less than 100 Ωcm; and/or 
 the semiconductor die is a silicon-on-insulator die; and/or 
 the semiconductor die includes at least one material selected from the group consisting of silicon, germanium, gallium nitride, gallium arsenide, indium phosphide, silicon carbide, sapphire, diamond, and diamond-like coating. 
 
     
     
       11. The electronic component of  claim 1 , further comprising an electrically conductive back end of line structure on a main surface of the semiconductor die opposing another main surface of the semiconductor die on the mold layer. 
     
     
       12. The electronic component of  claim 11 , wherein the back end of line structure is directly connected to the active area of the semiconductor die. 
     
     
       13. The electronic component of  claim 11 , further comprising at least one electrically conductive protrusion protruding beyond the back end of line structure. 
     
     
       14. The electronic component of  claim 1 , wherein the semiconductor die is a high frequency semiconductor die. 
     
     
       15. The electronic component of  claim 1 , wherein the mold layer is cured and has adhesive properties in an uncured state. 
     
     
       16. A package, comprising:
 the electronic component of  claim 1 , the electronic component comprising a dielectric layer as the mold layer; and 
 an encapsulant encapsulating at least part of the electronic component. 
 
     
     
       17. The package of  claim 16 , wherein the dielectric layer comprises a mold foil, and/or a curable layer, and/or a temperature curable layer. 
     
     
       18. The package of  claim 16 , further comprising:
 a carrier at least partially encapsulated by the encapsulant and electrically connected with the electronic component; and/or 
 an electrically conductive back end of line structure on a main surface of the semiconductor die and connected to an at least partially electrically conductive carrier, 
 wherein the encapsulant is a mold compound having different material properties than the dielectric layer. 
 
     
     
       19. The electronic component of  claim 1 , wherein the low ohmic semiconductor portion is a crystalline silicon portion, and wherein the high ohmic semiconductor portion is a high resistance silicon portion. 
     
     
       20. The electronic component of  claim 1 , wherein the low ohmic semiconductor portion and the high ohmic semiconductor portion are separated by a dielectric layer in between. 
     
     
       21. The electronic component of  claim 1 , wherein the low ohmic semiconductor portion has an electric resistivity in a range from 1 Ωcm to 10 Ωcm, and wherein the high ohmic semiconductor portion has an electric resistivity of at least 500 Ωcm. 
     
     
       22. A method of manufacturing electronic components, the method comprising:
 providing a semiconductor wafer comprising a plurality of semiconductor dies each comprising a low ohmic semiconductor portion and a high ohmic semiconductor portion, wherein each of the low ohmic semiconductor portions has an active area; 
 arranging the high ohmic semiconductor portions on a mold layer; and 
 thereafter separating the semiconductor wafer and the mold layer into a plurality of separate electronic components each comprising at least one of the semiconductor dies and a portion of the mold layer. 
 
     
     
       23. The method of  claim 22 , further comprising:
 temporarily connecting a carrier wafer to the semiconductor wafer before the arranging, and removing the carrier wafer from the semiconductor wafer before the separating; and/or 
 thinning the semiconductor wafer by removing material at least of the high ohmic semiconductor portions, before connecting the semiconductor wafer to the mold layer; and/or 
 temporarily connecting a dicing foil to the mold layer before or after the arranging, and removing the dicing foil from the electronic components during or after the separating; and/or 
 embedding electrically conductive protrusions on an electrically conductive back end of line structure on a main surface of the semiconductor wafer in a temporary adhesive structure, the temporary adhesive structure connecting the semiconductor wafer with a carrier wafer; and/or 
 separating by at least one of mechanically sawing, laser sawing and etching; and/or 
 encapsulating each electronic component by an encapsulant after the separating.