Gate driver having input and output sides galvanically isolated from one another

Abstract

A gate driver includes: an input pin for receiving switching control information from a controller; an output pin for driving a control terminal of a power transistor; a power supply pin for receiving power from an external supply; an input side electrically connected to the input pin; an output side electrically connected to the output pin and the power supply pin; and an isolation structure galvanically isolating the input side and the output side from one another. The output side is configured to transfer a fraction of the power received at the power supply pin to the input side over the isolation structure for powering the input side. The input side is configured to convey the switching control information received at the input pin to the output side over the isolation structure. A power electronic system that includes the gate driver is also described.

What is claimed is: 
     
       1. A gate driver, comprising:
 an input pin for receiving switching control information from a controller; 
 an output pin for driving a control terminal of a power transistor; 
 a power supply pin for receiving power from an external supply; 
 an input side electrically connected to the input pin; 
 an output side electrically connected to the output pin and the power supply pin; and 
 an isolation structure galvanically isolating the input side and the output side from one another, 
 wherein the output side is configured to transfer a fraction of the power received at the power supply pin to the input side over the isolation structure for powering the input side, 
 wherein the input side is configured to convey the switching control information received at the input pin to the output side over the isolation structure. 
 
     
     
       2. The gate driver of  claim 1 , wherein the input side is configured to convey the switching control information received at the input pin to the output side over the isolation structure by modulating a load impedance for the input side as seen by the output side. 
     
     
       3. The gate driver of  claim 2 , wherein the fraction of the power transferred from the output side to the input side over the isolation structure includes a time-varying component having a slope effected by the modulated load impedance, and wherein the output side is configured to detect the slope of the time-varying component and drive the output pin based on the detected slope. 
     
     
       4. The gate driver of  claim 3 , wherein the switching control information received at the input pin is a PWM (pulse width modulation) signal having a logic low level and a logic high level, wherein the input side is configured to change the load impedance each time the PWM signal transitions from the logic low level to the logic high level or from the logic high level to the logic low level, wherein the output side is configured to drive the output pin to a first voltage level if the detected slope is below a threshold and to a second voltage level if the detected slope exceeds the threshold, wherein the first voltage level corresponds to the logic low level of the PWM signal, and wherein the second voltage level corresponds to the logic high level of the PWM signal. 
     
     
       5. The gate driver of  claim 1 , further comprising:
 a sensor pin at the output side for receiving a sensed parameter of the power transistor, 
 wherein the output side is configured to convey the sensed parameter received at the sensor pin to the input side over the isolation structure. 
 
     
     
       6. The gate driver of  claim 5 , wherein the fraction of the power transferred from the output side to the input side over the isolation structure has a time-varying component, and wherein a pulse generator on the output side has an adjustable switching frequency and/or amplitude for conveying the sensed parameter received at the sensor pin to the input side over the isolation structure. 
     
     
       7. The gate driver of  claim 6 , wherein a frequency and/or amplitude detector on the input side is configured to detect the sensed parameter conveyed from the output side to the input side over the isolation structure based on the switching frequency and/or amplitude. 
     
     
       8. The gate driver of  claim 6 , further comprising:
 an error detection pin at the input side for outputting an error detection signal, 
 wherein the input side is configured to generate the error detection signal if the sensed parameter conveyed from the output side to the input side over the isolation structure indicates an error. 
 
     
     
       9. The gate driver of  claim 8 , further comprising:
 a restart pin at the input side for receiving a restart signal, 
 wherein the input side is configured to clear an indication of the error and restart operation of the gate driver. 
 
     
     
       10. The gate driver of  claim 1 , wherein the input side and the output side are each configured to implement a calibration process during startup of the gate driver. 
     
     
       11. The gate driver of  claim 10 , wherein as part of the calibration process, the output side is configured to begin transfer of the fraction of the power received at the power supply pin to the input side over the isolation structure, monitor an input-side load impedance as seen by the output side for settling, monitor changes in the input-side load impedance after settling, and initiate switching frequency modulation with the input side over the isolation structure, and wherein as part of the calibration process, the input side is configured to stabilize an internal supply of the input side based on the fraction of the power transferred from the output side to the input side over the isolation structure, activate modulation of the input-side load impedance, and detect the switching frequency modulation initiated by the output side. 
     
     
       12. The gate driver of  claim 1 , wherein the isolation structure is a coreless transformer comprising a first coil electrically connected to the input side, a second coil electrically connected to the output side, and an isolation barrier separating the first coil and the second coil from one another. 
     
     
       13. The gate driver of  claim 1 , wherein the isolation structure is a capacitive coupler comprising a first field plate electrically connected to the input side, a second field plate electrically connected to the output side, and an isolation barrier separating the first field plate and the second field plate from one another. 
     
     
       14. A power electronic system, comprising:
 a power transistor module; 
 a controller; 
 a power supply; and 
 a gate driver comprising:
 an input pin for receiving switching control information from the controller; 
 an output pin for driving a control terminal of a power transistor included in the power transistor module; 
 a power supply pin for receiving power from the power supply; 
 an input side electrically connected to the input pin; 
 an output side electrically connected to the output pin and the power supply pin; and 
 an isolation structure galvanically isolating the input side and the output side from one another such that the controller is galvanically isolated from the power transistor module, 
 wherein the output side is configured to transfer a fraction of the power received at the power supply pin to the input side over the isolation structure for powering the input side, 
 wherein the input side is configured to convey the switching control information received at the input pin to the output side over the isolation structure. 
 
 
     
     
       15. The power electronic system of  claim 14 , wherein the input side of the gate driver is configured to convey the switching control information received at the input pin of the gate driver to the output side of the gate driver over the isolation structure by modulating a load impedance for the input side of the gate driver as seen by the output side of the gate driver. 
     
     
       16. The power electronic system of  claim 15 , wherein the fraction of the power transferred from the output side of the gate driver to the input side of the gate driver over the isolation structure includes a time-varying component having a slope effected by the modulated load impedance, and wherein the output side of the gate driver is configured to detect the slope of the time-varying component and drive the output pin based on the detected slope. 
     
     
       17. The power electronic system of  claim 16 , wherein the switching control information received at the input pin of the gate driver is a PWM (pulse width modulation) signal having a logic low level and a logic high level, wherein the input side of the gate driver is configured to change the load impedance each time the PWM signal transitions from the logic low level to the logic high level or from the logic high level to the logic low level, wherein the output side of the gate driver is configured to drive the output pin of the gate driver to a first voltage level if the detected slope is below a threshold and to a second voltage level if the detected slope exceeds the threshold, wherein the first voltage level corresponds to the logic low level of the PWM signal, and wherein the second voltage level corresponds to the logic high level of the PWM signal. 
     
     
       18. The power electronic system of  claim 14 , wherein the gate driver further comprises a sensor pin at the output side of the gate driver for receiving a sensed parameter of the power transistor, and wherein the output side of the gate driver is configured to convey the sensed parameter received at the sensor pin of the gate driver to the input side of the gate driver over the isolation structure. 
     
     
       19. The power electronic system of  claim 18 , wherein the fraction of the power transferred from the output side of the gate driver to the input side of the gate driver over the isolation structure has a time-varying component, and wherein a pulse generator on the output side of the gate driver has an adjustable switching frequency and/or amplitude for conveying the sensed parameter received at the sensor pin of the gate driver to the input side of the gate driver over the isolation structure. 
     
     
       20. The power electronic system of  claim 19 , wherein a frequency and/or amplitude detector on the input side of the gate driver is configured to detect the sensed parameter conveyed from the output side of the gate driver to the input side of the gate driver over the isolation structure based on the switching frequency and/or amplitude. 
     
     
       21. The power electronic system of  claim 14 , wherein the input side of the gate driver and the output side of the gate driver are each configured to implement a calibration process during startup of the gate driver. 
     
     
       22. The power electronic system of  claim 21 , wherein as part of the calibration process, the output side of the gate driver is configured to begin transfer of the fraction of the power received at the power supply pin of the gate driver to the input side of the gate driver over the isolation structure, monitor an input-side load impedance as seen by the output side of the gate driver for settling, monitor changes in the input-side load impedance after settling, and initiate switching frequency modulation with the input side of the gate driver over the isolation structure, and wherein as part of the calibration process, the input side of the gate driver is configured to stabilize an internal supply of the input side of the gate driver based on the fraction of the power transferred from the output side of the gate driver to the input side of the gate driver over the isolation structure, activate modulation of the input-side load impedance, and detect the switching frequency modulation initiated by the output side of the gate driver.