Apparatus and method for improving data input/output speed of non-volatile memory device

Abstract

A voltage generation circuit includes a noise attenuation circuit configured to attenuate a noise of a second power voltage which has a level that is at least two times higher than that of a first power voltage, and a multi-stage voltage pump configured to receive a noise-attenuated second power voltage from the noise attenuation circuit and generate at least one of plural target voltages, each target voltage having a different level. The first and second power voltages are individually input from an external device via different pins or pads.

What is claimed is: 
     
       1. A voltage generation circuit, comprising:
 a noise attenuation circuit configured to attenuate a noise of a second power voltage which has a level that is at least two times higher than that of a first power voltage, wherein the first and second power voltages are individually input from an external device via different pins or pads; and 
 a multi-stage voltage pump configured to receive a noise-attenuated second power voltage from the noise attenuation circuit and generate at least one of plural target voltages, each target voltage having a different level, 
 wherein the multi-stage voltage pump comprises: 
 plural unit voltage pumps serially connected to each other and configured to receive the second power voltage; and 
 at least one diode including a cathode coupled between an output terminal and an input terminal of neighboring unit voltage pumps of the plural unit voltage pumps, and an anode coupled to the second power voltage, wherein the at least one diode is configured to maintain a voltage level on the output terminal and the input terminal of the neighboring unit voltage pumps to avoid application of a breakdown voltage of a transistor included in the neighboring unit voltage pumps. 
 
     
     
       2. The voltage generation circuit according to  claim 1 , wherein the noise attenuation circuit is always coupled to the pins or pads while the voltage generation circuit generates the at least one of the plural target voltages. 
     
     
       3. The voltage generation circuit according to  claim 1 , wherein the noise attenuation circuit comprises a rectifier including a diode arranged between input and output terminals, and a capacitor coupled to the output terminal. 
     
     
       4. The voltage generation circuit according to  claim 1 , wherein the noise attenuation circuit comprises a low pass filter including a resistor arranged between input and output terminals, and a capacitor coupled to the output terminal. 
     
     
       5. The voltage generation circuit according to  claim 1 , wherein the plural target voltages comprises:
 a program voltage used for programming a data item in a non-volatile memory cell; 
 an erase voltage used for erasing the data item in the non-volatile memory cell; and 
 a read voltage used for reading the data item in the non-volatile memory cell. 
 
     
     
       6. A memory device, comprising:
 a memory group including a plurality of non-volatile memory cells; 
 a voltage generation circuit configured to generate at least one of plural target voltages used for inputting or outputting a data item to or from the memory group; and 
 plural buffers configured to temporarily store the data item output from the memory group or to be input to the memory group, 
 wherein the voltage generation circuit comprises: 
 a noise attenuation circuit configured to attenuate a noise of a second power voltage which has a level that is at least two times higher than that of a first power voltage, wherein the first and second power voltages are individually input from an external device via different pins or pads; and 
 a multi-stage voltage pump configured to receive a noise-attenuated second power voltage from the noise attenuation circuit and generate the at least one of plural target voltages, each target voltage having a different level, 
 wherein the multi-stage voltage pump comprises: 
 plural unit voltage pumps serially connected to each other and configured to receive the second power voltage; and 
 at least one diode including a cathode coupled between an output terminal and an input terminal of neighboring unit voltage pumps of the plural unit voltage pumps, and an anode coupled to the second power voltage, wherein the at least one diode is configured to maintain a voltage level on the output terminal and the input terminal of the neighboring unit voltage pumps to avoid application of a breakdown voltage of a transistor included in the neighboring unit voltage pumps. 
 
     
     
       7. The memory device according to  claim 6 , wherein the noise attenuation circuit is always coupled to the pins or pads while the voltage generation circuit generates the at least one of the plural target voltages. 
     
     
       8. The memory device according to  claim 6 , wherein the noise attenuation circuit comprises a rectifier including a diode arranged between input and output terminals, and a capacitor coupled to the output terminal. 
     
     
       9. The memory device according to  claim 6 , wherein the noise attenuation circuit comprises a low pass filter including a resistor arranged between input and output terminals, and a capacitor coupled to the output terminal. 
     
     
       10. The memory device according to  claim 6 , wherein the plural target voltages comprises:
 a program voltage used for programming a data item in a non-volatile memory cell; 
 an erase voltage used for erasing the data item in the non-volatile memory cell; and 
 a read voltage used for reading the data item in the non-volatile memory cell. 
 
     
     
       11. The memory device according to  claim 6 ,
 wherein the plural buffers are coupled to the first power voltage and a first ground voltage corresponding to the first power voltage, while the multi-stage voltage pump is coupled to the second power voltage and a second ground voltage corresponding to the second power voltage, and 
 wherein a node of the first ground voltage is electrically isolated from a node of the second ground voltage. 
 
     
     
       12. The memory device according to  claim 6 ,
 wherein the plural buffers are coupled to respective bit lines of the memory group, and 
 wherein the plural buffers are coupled to respective buses to transfer the data item output from the memory group. 
 
     
     
       13. The memory device according to  claim 12 , wherein the plural buffers are coupled to a data serializer via the respective buses, and the plural buffers transfer the data item via the respective buses without any wait time. 
     
     
       14. A semiconductor device, comprising:
 a first pin or pad configured to receive a first power voltage input from an external device; 
 a second pin or pad configured to receive a second power voltage input from an external device, wherein the second power voltage has a level that is at least two times higher than that of a first power voltage; 
 a multi-stage voltage pump configured to receive the second power voltage and generate at least one of plural target voltages, each target voltage having a different level; and 
 a noise attenuation circuit, arranged between the second pin or pad and the multi-stage voltage pump and configured to attenuate a noise of the second power voltage 
 wherein the multi-stage voltage pump comprises: 
 plural unit voltage pumps serially connected to each other and configured to receive a noise-attenuated second power voltage; and 
 at least one diode including a cathode coupled between an output terminal and an input terminal of neighboring unit voltage pumps of the plural unit voltage pumps, and an anode coupled to the second power voltage, wherein the at least one diode is configured to maintain a voltage level on the output terminal and the input terminal of the neighboring unit voltage pumps to avoid application of a breakdown voltage of a transistor included in the neighboring unit voltage pumps.