Driving backplane and display panel

Abstract

A driving backplane includes: a base, and pixel driving circuits, data lines and first power supply voltage lines that are disposed on the base. The pixel driving circuit is electrically connected to a data line and a first power supply voltage line. The pixel driving circuit includes a driving transistor, a first switching transistor, and a first conductive pattern located on a side, away from the base, of a gate of the driving transistor and a gate of the first switching transistor. The first conductive pattern is electrically connected to the gate of the driving transistor through a first via, and to a second electrode of the first switching transistor through a second via. An orthogonal projection of the first conductive pattern on the base is located within an orthogonal projection of the first power supply voltage line on the base.

What is claimed is: 
     
       1. A driving backplane having a plurality of sub-pixel regions, the driving backplane comprising:
 a base; 
 a plurality of pixel driving circuits disposed on the base, a pixel driving circuit of the plurality of pixel driving circuits being disposed in one of the plurality of sub-pixel regions; 
 a plurality of data lines and a plurality of first power supply voltage lines disposed on the base; wherein 
 the pixel driving circuit is electrically connected to a data line, and is further electrically connected to a first power supply voltage line; the data line and the first power supply voltage line are disposed on a side, away from the base, of the pixel driving circuit, and the data line and the first power supply voltage line are arranged in a same layer and insulated from each other; and 
 the pixel driving circuit includes:
 a driving transistor; 
 a first switching transistor; and 
 a first conductive pattern, the first conductive pattern being located on a side, away from the base, of a gate of the driving transistor and a gate of the first switching transistor; wherein 
 the first conductive pattern is electrically connected to the gate of the driving transistor through a first via disposed between the first conductive pattern and the gate of the driving transistor, and the first conductive pattern is electrically connected to a second electrode of the first switching transistor through a second via disposed between the first conductive pattern and the second electrode of the first switching transistor; and 
 an orthogonal projection of the first conductive pattern on the base is located within an orthogonal projection of the first power supply voltage line on the base. 
 
 
     
     
       2. The driving backplane according to  claim 1 , wherein
 an active pattern of the first switching transistor includes at least one first channel region, and a first source region and a first drain region that are located on both sides of the at least one first channel region; at least one gate of the first switching transistor is disposed on a side, away from the base, of the at least one first channel region, and an orthogonal projection of a portion of the active pattern of the first switching transistor in a first channel region on the base overlaps with an orthogonal projection of a corresponding gate of the first switching transistor on the base; and portions of the active pattern of the first switching transistor that are located in the first source region and the first drain region are served as portions of a first electrode and a second electrode of the first switching transistor; and 
 an orthogonal projection of the second electrode of the first switching transistor on the base is located within the orthogonal projection of the first power supply voltage line on the base. 
 
     
     
       3. The driving backplane according to  claim 2 , wherein an active pattern of the driving transistor includes a second channel region, and a second source region and a second drain region that are located on both sides of the second channel region; an orthogonal projection of a portion of the active pattern of the driving transistor in the second channel region on the base overlaps with an orthogonal projection of the gate of the driving transistor on the base; and portions of the active pattern of the driving transistor that are located in the second source region and the second drain region are served as portions of a first electrode and a second electrode of the driving transistor; and
 the active pattern of the driving transistor and the active pattern of the first switching transistor are disposed in a same layer. 
 
     
     
       4. The driving backplane according to  claim 3 , wherein the pixel driving circuit further includes a capacitor and a second conductive pattern; wherein
 the gate of the driving transistor is used as a first storage electrode of the capacitor; and a second storage electrode of the capacitor is located on a side, away from the base, of the first storage electrode; 
 the second conductive pattern is electrically connected to the second storage electrode through at least one third via disposed between the second conductive pattern and the second storage electrode, and the second conductive pattern is electrically connected to the first power supply voltage line through at least a second sub-via disposed between the second conductive pattern and the first power supply voltage line; 
 the second conductive pattern and the first conductive pattern are disposed in a same layer, and the first power supply voltage line is disposed at a side, away from the second storage electrode, of a layer where the second conductive pattern and the first conductive pattern are located; and 
 the second storage electrode has a hollow region, and an orthogonal projection of the first via on the base is located within the hollow region. 
 
     
     
       5. The driving backplane according to  claim 4 , wherein the second conductive pattern is electrically connected to the first power supply voltage line through the second sub-via and a first sub-via disposed between the second conductive pattern and the first power supply voltage line;
 the second sub-via is located on a side, away from the base, of the first sub-via; the second sub-via and the first sub-via are communicated with each other and constitute a fourth via; and 
 the second sub-via is disposed in an organic insulating layer, and the first sub-via is disposed in an inorganic insulating layer. 
 
     
     
       6. The driving backplane according to  claim 4 , wherein in sub-pixel regions in a same row in the plurality of sub-pixel regions, second storage electrodes of capacitors in pixel driving circuits of any adjacent sub-pixel regions are electrically connected to each other. 
     
     
       7. The driving backplane according to  claim 4 , further comprising initialization signal lines disposed on the base; wherein
 the pixel driving circuit further includes a third conductive pattern; wherein 
 the first electrode of the first switching transistor is electrically connected to the third conductive pattern through a sixth via disposed between the first electrode of the first switching transistor and the third conductive pattern, the third conductive pattern is electrically connected to an initialization signal line through a seventh via disposed between the third conductive pattern and the initialization signal line, and the initialization signal line and the second storage electrode are disposed in a same layer; and 
 the third conductive pattern and the second conductive pattern are disposed in a same layer. 
 
     
     
       8. The driving backplane according to  claim 7 , further comprising gate lines disposed on the base; wherein
 the pixel driving circuit further includes a second switching transistor and a fourth conductive pattern; wherein 
 a portion of a gate line is served as a gate of the second switching transistor, and the gate line and the gate of the driving transistor are disposed in a same layer; 
 an active pattern of the second switching transistor includes a third channel region, and a third source region and a third drain region that are located on both sides of the third channel region; an orthogonal projection of the gate of the second switching transistor on the base overlaps with an orthogonal projection of a portion of the active pattern of the second switching transistor in the third channel region on the base, and portions of the active pattern of the second switching transistor that are located in the third source region and the third drain region are served as a first electrode and a second electrode of the second switching transistor; 
 the first electrode of the second switching transistor is electrically connected to the fourth conductive pattern through an eighth via disposed between the first electrode of the second switching transistor and the fourth conductive pattern, and the fourth conductive pattern is electrically connected to the data line through at least a fourth sub-via disposed between the fourth conductive pattern and the data line; 
 the second electrode of the second switching transistor is electrically connected to the first electrode of the driving transistor; and 
 the fourth conductive pattern is disposed in a same layer as the first conductive pattern and the second conductive pattern. 
 
     
     
       9. The driving backplane according to  claim 8 , wherein the fourth conductive pattern is electrically connected to the data line through the fourth sub-via and a third sub-via disposed between the fourth conductive pattern and the data line; the fourth sub-via is located on a side, away from the base, of the third sub-via; the fourth sub-via and the third sub-via are communicated with each other and constitute a ninth via; and
 the fourth sub-via is disposed in an organic insulating layer, and the third sub-via is disposed in an inorganic insulating layer. 
 
     
     
       10. The driving backplane according to  claim 8 , wherein the pixel driving circuit further includes a third switching transistor; wherein
 a portion of the gate line is served as a gate of the third switching transistor; 
 an active pattern of the third switching transistor includes a fourth channel region, and a fourth source region and a fourth drain region that are located on both sides of the fourth channel region; an orthogonal projection of the gate of the third switching transistor on the base overlaps with an orthogonal projection of a portion of the active pattern of the third switching transistor in the fourth channel region on the base, and portions of the active pattern of the third switching transistor that are located in the fourth source region and the fourth drain region are served as a first electrode and a second electrode of the third switching transistor; 
 the first electrode of the third switching transistor is electrically connected to the second electrode of the driving transistor; and 
 the second electrode of the third switching transistor is electrically connected to the second electrode of the first switching transistor. 
 
     
     
       11. The driving backplane according to  claim 10 , wherein the first electrode of the third switching transistor is electrically connected to the second electrode of the driving transistor through a connection portion, and the second electrode of the third switching transistor is electrically connected to the second electrode of the first switching transistor through another connection portion. 
     
     
       12. The driving backplane according to  claim 10 , further comprising light-emitting control lines disposed on the base; wherein
 the pixel driving circuit further includes a fourth switching transistor; wherein 
 a portion of a light-emitting control line is served as a gate of the fourth switching transistor, and the light-emitting control line is disposed in a same layer as the gate of the driving transistor; 
 an active pattern of the fourth switching transistor includes a fifth channel region, and a fifth source region and a fifth drain region that are located on both sides of the fifth channel region; an orthogonal projection of the gate of the fourth switching transistor on the base overlaps with an orthogonal projection of a portion of the active pattern of the fourth switching transistor in the fifth channel region on the base, and portions of the active pattern of the fourth switching transistor that are located in the fifth source region and the fifth drain region are served as a first electrode and a second electrode of the fourth switching transistor; 
 the first electrode of the fourth switching transistor is electrically connected to the second conductive pattern through an eleventh via disposed between the first electrode of the fourth switching transistor and the second conductive pattern; and 
 the second electrode of the fourth switching transistor and the first electrode of the driving transistor are connected and formed as an integral structure. 
 
     
     
       13. The driving backplane according to  claim 12 , wherein the pixel driving circuit further includes a fifth switching transistor, a fifth conductive pattern and a sixth conductive pattern; wherein
 a portion of the light-emitting control line is served as a gate of the fifth switching transistor; 
 an active pattern of the fifth switching transistor includes a sixth channel region, and a sixth source region and a sixth drain region that are located on both sides of the sixth channel region; an orthogonal projection of the gate of the fifth switching transistor on the base overlaps with an orthogonal projection of a portion of the active pattern of the fifth switching transistor in the sixth channel region on the base, and portions of the active pattern of the fifth switching transistor that are located in the sixth source region and the sixth drain region are served as a first electrode and a second electrode of the fifth switching transistor; 
 the first electrode of the fifth switching transistor and the second electrode of the driving transistor are connected and formed as an integral structure; 
 the second electrode of the fifth switching transistor is electrically connected to the fifth conductive pattern through a twelfth via disposed between the second electrode of the fifth switching transistor and the fifth conductive pattern, and the fifth conductive pattern is electrically connected to the sixth conductive pattern through at least a sixth sub-via disposed between the fifth conductive pattern and the sixth conductive pattern; the sixth conductive pattern is configured to be electrically connected to a light-emitting device; 
 the fifth conductive pattern and the second conductive pattern are disposed in a same layer; and 
 the sixth conductive pattern is disposed in a same layer as the data line and the first power supply voltage line. 
 
     
     
       14. The driving backplane according to  claim 13 , wherein the fifth conductive pattern is electrically connected to the sixth conductive pattern through the sixth sub-via and a fifth sub-via disposed between the fifth conductive pattern and the sixth conductive pattern;
 the sixth sub-via is located on a side, away from the base, of the fifth sub-via; the sixth sub-via and the fifth sub-via are communicated with each other and constitute a thirteenth via; and 
 the sixth sub-via is disposed in an organic insulating layer, and the fifth sub-via is disposed in an inorganic insulating layer. 
 
     
     
       15. The driving backplane according to  claim 13 , further comprising reset signal lines disposed on the base; wherein
 the pixel driving circuit further includes a sixth switching transistor; wherein 
 a portion of a reset signal line is served as a gate of the sixth switching transistor; 
 an active pattern of the sixth switching transistor includes a seventh channel region, and a seventh source region and a seventh drain region that are located on both sides of the seventh channel region; an orthogonal projection of the gate of the sixth switching transistor on the base overlaps with an orthogonal projection of a portion of the active pattern of the sixth switching transistor in the seventh channel region on the base, and portions of the active pattern of the sixth switching transistor that are located in the seventh source region and the seventh drain region are served as a first electrode and a second electrode of the sixth switching transistor; and 
 the first electrode of the sixth switching transistor is electrically connected to the first electrode of the first switching transistor. 
 
     
     
       16. The driving backplane according to  claim 1 , wherein pixel driving circuits located in sub-pixel regions in a same column of the plurality of sub-pixel regions are electrically connected to two data lines; and
 a first power supply voltage line electrically connected to the pixel driving circuits that are located in the sub-pixels in the same column is located between the two data lines. 
 
     
     
       17. The driving backplane according to  claim 1 , wherein pixel driving circuits located in adjacent two sub-pixel regions in a same row in the plurality of sub-pixel regions are electrically connected to two first power supply voltage lines, respectively; and
 two data lines are located between the two first power supply voltage lines. 
 
     
     
       18. The driving backplane according to  claim 1 , wherein pixel driving circuits in any adjacent sub-pixel regions of sub-pixel regions in a same row are arranged in mirror symmetry. 
     
     
       19. A display panel, comprising:
 the driving backplane according to  claim 1 ; and 
 a light-emitting device disposed in the sub-pixel region of the plurality of sub-pixel regions on the driving backplane, the light-emitting device being electrically connected to the pixel driving circuit. 
 
     
     
       20. The display panel according to  claim 19 , wherein the driving backplane further has a peripheral region;
 the display panel further comprises a scan driver, a light-emitting driver, a data driver, a timing controller, and a plurality of multiplexers disposed in the peripheral region; and each multiplexer corresponds to pixel driving circuits in sub-pixel regions in a column of sub-pixel regions of the plurality of sub-pixel regions; wherein 
 the scan driver is electrically connected to a plurality of gate lines and the timing controller, and the scan driver is configured to output gate scan signals to the plurality of gate lines one by one in response to a signal received from the timing controller; 
 the light-emitting driver is electrically connected to a plurality of light-emitting control lines and the timing controller, and the light-emitting driver is configured to output light-emitting control signals to the light-emitting control lines one by one in response to the signal received from the timing controller; 
 the data driver is electrically connected to the plurality of multiplexers and the timing controller, and the data driver is configured to output data signals to the plurality of multiplexers in response to the signal received from the timing controller; and 
 each multiplexer is further electrically connected to the timing controller and two data lines that are electrically connected to pixel driving circuits in sub-pixel regions in a same column corresponding to each multiplexer, and each multiplexer is configured to transmit a data signal from the data driver to one of the two data lines and another of the two data lines in different time periods in response to the signal received from the timing controller.