Resistance element and its manufacturing method

Abstract

A resistance element includes a plurality of resistance chips stacked vertically, each of the plurality of resistance chips including a semiconductor substrate, one or more resistance layers on a field insulating film, a pad forming electrode on electrically connected to the one or more resistance layers, a relay wiring on the interlayer insulating film, laterally separated from the pad forming electrode, electrically connected to another end of at least one of the one or more resistance layers on one end and to a semiconductor substrate on another end, and a back surface electrode at a bottom of the semiconductor substrate, making ohmic contact with the semiconductor substrate, wherein the plurality of resistance chips have the same planar outer shape, and are stacked one over another so as to constitute a resistor as a whole.

What is claimed is: 
     
       1. A resistance element, comprising:
 a plurality of resistance chips stacked vertically, each of the plurality of resistance chips including:
 a semiconductor substrate, 
 a field insulating film on the semiconductor substrate, 
 one or more resistance layers on the field insulating film, 
 an interlayer insulating film covering the field insulating film and the one or more resistance layers, 
 a pad forming electrode on the interlayer insulating film and electrically connected to one end of at least one of the one or more resistance layers, 
 a relay wiring on the interlayer insulating film, laterally separated from the pad forming electrode, one end of the relay wiring being electrically connected to one end of at least one of the one or more resistance layers other than said one end of at least one of the one or more resistance layers to which the pad forming electrode is electrically connected, another end of the relay wiring making ohmic contact with the semiconductor substrate, and 
 a back surface electrode at a bottom of the semiconductor substrate, making ohmic contact with the semiconductor substrate, 
 
 wherein the plurality of resistance chips have the same planar outer shape, and are stacked one over another such that the back surface electrode of the resistance chip stacked on top of another resistance chip is electrically connected to the pad forming electrode of the another resistance chip immediately therebelow so that a current path between the pad forming electrode on an uppermost resistance chip and the back surface electrode of a lowermost resistance chip constitutes a resistor. 
 
     
     
       2. The resistance element according to  claim 1 ,
 wherein said another resistance chip immediately therebelow further includes a plating layer on the pad forming electrode, and 
 wherein the back surface electrode of the resistance chip stacked on top is bonded to the plating layer of the another resistance chip immediately therebelow via a bonding layer. 
 
     
     
       3. The resistance element according to  claim 2 , wherein the bonding layer is provided in a plurality at a plurality of locations separated from each other. 
     
     
       4. The resistance element according to  claim 2 , wherein the bonding layer is provided at a center of the planar pattern of the resistance chips. 
     
     
       5. The resistance element according to  claim 2 , wherein the bonding layer is in contact with an insulating layer provided between the back surface electrode of the resistance chip on top and the plating layer of the another resistance chip immediately therebelow. 
     
     
       6. The resistance element according to  claim 1 , wherein the plurality of resistance chips have the same structure as each other. 
     
     
       7. The resistance element according to  claim 1 , wherein the plurality of resistance chips have different resistance values from each other. 
     
     
       8. The resistance element according to  claim 1 , wherein each of the plurality of resistance chips further includes a protective insulating film on the pad forming electrode, the relay wiring, and the interlayer insulating film. 
     
     
       9. A method for manufacturing a resistance element, comprising:
 preparing a plurality of resistance chips, each of the plurality of resistance chips having the same planar outer shape and including:
 a semiconductor substrate, 
 a field insulating film on the semiconductor substrate, 
 one or more resistance layers on the field insulating film, 
 an interlayer insulating film covering the field insulating film and the one or more resistance layers, 
 a pad forming electrode on the interlayer insulating film and electrically connected to one end of at least one of the one or more resistance layers, 
 a relay wiring on the interlayer insulating film, laterally separated from the pad forming electrode, one end of the relay wiring being electrically connected to one end of at least one of the one or more resistance layers other than said one end of at least one of the one or more resistance layers to which the pad forming electrode is electrically connected, another end of the relay wiring making ohmic contact with the semiconductor substrate, and 
 a back surface electrode at a bottom of the semiconductor substrate, making ohmic contact with the semiconductor substrate; and 
 
 stacking the plurality of resistance elements vertically such that the back surface electrode of the resistance chip stacked on top of another resistance chip is electrically connected to the pad forming electrode of the another resistance chip immediately therebelow so that a current path between the pad forming electrode on an uppermost resistance chip and the back surface electrode of a lowermost resistance chip constitutes a resistor. 
 
     
     
       10. The method according to  claim 9 , wherein the stacking of the plurality of resistance elements vertically includes forming a plating layer on the pad forming electrode of the another resistance chip immediately therebelow, and bonding the back surface electrode of the resistance chip stacked on top to the plating layer of the another resistance chip immediately therebelow via a bonding layer. 
     
     
       11. The method according to  claim 10 ,
 wherein each of the plurality of resistance chips further includes a protective insulating film on the pad forming electrode, the relay wiring, and the interlayer insulating film, and 
 wherein the method further comprises filling a space between the back surface electrode of the resistance chip stacked on top and the plating layer and the protective insulating film of the another resistance chip immediately therebelow with a sealing material.