Dynamic channel mapping for a memory system

Abstract

Methods, systems, and devices for dynamic channel mapping for a memory system are described. In one example, the memory system may include a memory device having a first set of pins that are associated with a channel, and a host device, coupled with the memory device, having a second set of pins that are associated with the channel. The host device may include a controller configured to receive signaling from the memory device for a channel mapping operation, determine a channel mapping (e.g., a mapping of pins, a mapping between pins of the channel and information positions of the channel) based at least in part on the received signaling, and communicate information with the memory device via the channel based at least in part on the determined channel mapping.

What is claimed is: 
     
       1. A method, comprising:
 receiving, from a memory device, over one or more pins of a host device that are associated with a data channel, signaling for a channel mapping operation; 
 determining, for a pin mapper of the host device based at least in part on the received signaling, a mapping between each pin of the one or more pins of the host device and a respective one of a plurality of pins of the memory device, the pin mapper configured to support a dynamic mapping between the one or more pins of the host device and the plurality of pins of the memory device; and 
 communicating information via the data channel based at least in part on the determined mapping for the pin mapper of the host device. 
 
     
     
       2. The method of  claim 1 , wherein the plurality of pins of the memory device comprises a first subset of one or more pins and a second subset of one or more pins, and determining the mapping comprises:
 determining whether a subset of one or more of the pins of the host device is coupled with the first subset or the second subset. 
 
     
     
       3. The method of  claim 2 , wherein the first subset of one or more pins is a first byte-level subset and the second subset of one or more pins is a second byte-level subset, and determining the mapping comprises:
 determining whether a byte-level subset of the pins of the host device corresponds to the first byte-level subset or the second byte-level subset. 
 
     
     
       4. The method of  claim 1 , wherein the one or more pins of the host device comprises a first subset of one or more pins and a second subset of one or more pins, and receiving the signaling comprises:
 receiving first signaling indicative of a first logic state over the first subset of one or more pins; and 
 receiving second signaling indicative of a second logic state over the second subset of one or more pins. 
 
     
     
       5. The method of  claim 1 , wherein determining the mapping comprises:
 mapping each of the plurality of pins of the memory device to a respective information position of the data channel. 
 
     
     
       6. The method of  claim 1 , further comprising:
 transmitting, by the host device, command signaling corresponding to a set of mode register values, wherein the received signaling is based at least in part on the set of mode register values. 
 
     
     
       7. The method of  claim 1 , wherein determining the mapping comprises:
 identifying respective logic values conveyed by one or more of the plurality of pins of the memory device; and 
 comparing the respective logic values of the one or more of the plurality of pins to a sequence of logic values. 
 
     
     
       8. The method of  claim 1 , further comprising:
 writing the mapping to memory included in the host device or to a second memory device coupled with the host device. 
 
     
     
       9. The method of  claim 1 , wherein the communicating is performed according to a faster signaling rate than the signaling associated with the channel mapping operation. 
     
     
       10. The method of  claim 1 , further comprising:
 initiating, by the host device, the channel mapping operation. 
 
     
     
       11. A method, comprising:
 identifying an initialization event for a memory device that includes a plurality of pins associated with a data channel having a plurality of information positions; 
 reading one or more mode register values configured for a channel mapping operation based at least in part on identifying the initialization event; and 
 transmitting signaling for the channel mapping operation to a host device over the plurality of pins based at least in part on the one or more mode register values, wherein the signaling for the channel mapping operation is configured for a pin mapper of the host device to map each of the plurality of pins to a respective information position of the data channel, the pin mapper configured to support a dynamic mapping between the plurality of pins and the plurality of information positions. 
 
     
     
       12. The method of  claim 11 , wherein the plurality of pins of the memory device comprises a first subset of one or more pins and a second subset of one or more pins, and transmitting the signaling comprises:
 transmitting first signaling indicative of a first logic state over the first subset of one or more pins; and 
 transmitting second signaling indicative of a second logic state over the second subset of one or more pins. 
 
     
     
       13. The method of  claim 12 , wherein the first subset of one or more pins is a single pin and the second subset of one or more pins is a plurality of pins. 
     
     
       14. The method of  claim 12 , wherein the first subset of one or more pins is a first byte-level subset and the second subset of one or more pins is a second byte-level sub set. 
     
     
       15. The method of  claim 12 , wherein transmitting the signaling comprises:
 transmitting, after transmitting the first signaling and the second signaling, third signaling indicative of the second logic state over the first subset of one or more pins; and 
 transmitting, after transmitting the first signaling and the second signaling, fourth signaling indicative of the first logic state over the second subset of one or more pins. 
 
     
     
       16. The method of  claim 11 , further comprising:
 receiving, from the host device, a set of one or more commands to write a set of values to a set of mode registers. 
 
     
     
       17. The method of  claim 11 , wherein the signaling is performed according to a slower signaling rate than communicating data with the host device over the data channel. 
     
     
       18. A system, comprising:
 a memory device comprising a first plurality of pins that are associated with a data channel; and 
 a host device, coupled with the memory device, comprising a second plurality of pins that are associated with the data channel, and a controller configured to:
 receive signaling from the memory device for a channel mapping operation over one or more of the second plurality of pins; 
 determine, for a pin mapper of the host device based at least in part on the received signaling, a mapping between a pin of the one or more of the second plurality of pins and a respective one of the first plurality of pins, the pin mapper configured to support a dynamic mapping between the first plurality of pins and the second plurality of pins; and 
 communicate information with the memory device via the data channel based at least in part on the determined mapping for the pin mapper of the host device. 
 
 
     
     
       19. The system of  claim 18 , wherein the one or more of the second plurality of pins comprises a first subset of one or more pins and a second subset of one or more pins, and, to receive the signaling from the memory device, the controller is configured to:
 receive first signaling indicative of a first logic state over the first subset of one or more pins; and 
 receive second signaling indicative of a second logic state over the second subset of one or more pins. 
 
     
     
       20. The system of  claim 18 , wherein, to determine the mapping, the controller is configured to:
 map each pin of the one or more of the second plurality of pins to a respective information position of the data channel. 
 
     
     
       21. The system of  claim 18 , wherein the controller is configured to:
 store the mapping to memory included in the host device or to a second memory device coupled with the host device. 
 
     
     
       22. An apparatus, comprising:
 a plurality of first pins of a host device associated with a data channel and configured for electronic communication with a memory device; 
 a pin mapper of the host device configured to support a dynamic mapping between the plurality of first pins and a plurality of second pins of the memory device; and 
 a controller configured to cause the apparatus to:
 receive, from the memory device, signaling for a channel mapping operation over the plurality of first pins; 
 determine, for the pin mapper based at least in part on the received signaling, a mapping between each first pin of the plurality of first pins and a respective one of the plurality of second pins of the memory device; and 
 communicate information with the memory device via the data channel based at least in part on the determined mapping for the pin mapper. 
 
 
     
     
       23. The apparatus of  claim 22 , wherein the plurality of second pins of the memory device comprises a first subset of one or more second pins and a second subset of one or more second pins, and, to determine the mapping, the controller is configured to cause the apparatus to:
 determine whether a subset of the plurality of first pins is coupled with the first subset of second pins or the second subset of second pins. 
 
     
     
       24. The apparatus of  claim 22 , wherein the plurality of first pins comprises a first subset of first pins and a second subset of first pins, and, to receive the signaling, the controller is configured to cause the apparatus to:
 receive first signaling indicative of a first logic state over the first subset of first pins; and 
 receive second signaling indicative of a second logic state over the second subset of first pins. 
 
     
     
       25. The apparatus of  claim 22 , wherein the controller is configured to cause the apparatus to:
 transmit command signaling corresponding to a set of mode register values, wherein the received signaling is based at least in part on the set of mode register values.