Anti-eclipse circuitry with tracking of floating diffusion reset level

Abstract

Imagers and associated devices and systems are disclosed herein. In one embodiment, an imager includes a pixel array and control circuitry operably coupled to the pixel array. The pixel array includes an imaging pixel configured to produce a reset signal and a non-imaging pixel configured to produce a nominal reset signal. The control circuity is configured to produce an output signal based at least in part on one of (a) the nominal reset signal when distortion at the imaging pixel exceeds a threshold and (b) the reset signal when distortion does not exceed the threshold.

I claim: 
     
       1. An imager, comprising:
 a pixel array comprising a non-imaging pixel, 
 wherein the imager is configured to:
 produce a reference voltage using (a) a nominal reset voltage produced at least in part by the non-imaging pixel and (b) an offset voltage, 
 determine that the imager is experiencing an eclipsing event, and 
 improve, based at least in part on the determination and the reference voltage, a quality of an image captured by the imager. 
 
 
     
     
       2. The imager of  claim 1 , wherein a light sensitive element of the non-imaging pixel is shielded from incident light. 
     
     
       3. The imager of  claim 1 , wherein a gate of a transfer transistor of the non-imaging pixel is permanently coupled to a voltage level such that the transfer transistor remains off and not conducting. 
     
     
       4. The imager of  claim 1 , wherein, to produce the reference voltage, the imager is configured to apply the offset voltage to the nominal reset voltage. 
     
     
       5. The imager of  claim 1 , wherein:
 the pixel array further comprises an imaging pixel; and 
 to determine that the imager is experiencing an eclipsing event, the imager is configured to determine that a reset signal voltage produced at least in part by the imaging pixel is below a threshold voltage. 
 
     
     
       6. The imager of  claim 1 , wherein:
 the pixel array further comprises an imaging pixel; and 
 to improve the quality of the image captured by the imager, the imager is configured to adjust, based at least in part on the reference voltage, a reset signal voltage produced at least in part by the imaging pixel. 
 
     
     
       7. The imager of  claim 6 , wherein the imaging pixel is proximate the non-imaging pixel in the pixel array. 
     
     
       8. The imager of  claim 6 , wherein the imaging pixel is immediately adjacent the non-imaging pixel in the pixel array or is formed over a same substrate as the non-imaging pixel. 
     
     
       9. The imager of  claim 6 , wherein, to adjust the reset signal voltage, the imager is configured to pull the reset signal voltage up to a correction voltage. 
     
     
       10. The imager of  claim 9 , further comprising a sample and hold circuit, wherein the sample and hold circuit is configured to sample and hold the correction voltage at least while the imaging pixel is outputting the reset signal voltage. 
     
     
       11. The imager of  claim 1 , wherein:
 the pixel array further comprises an imaging pixel; and 
 to improve the quality of the image captured by the imager, the imager is configured to adjust an image signal corresponding to the imaging pixel and to the image such that the image signal does not correspond to a dark pixel in the image at least when bright light is incident upon the imaging pixel. 
 
     
     
       12. The imager of  claim 1 , wherein:
 the imager further comprises a reference voltage generator; 
 the reference voltage generator includes:
 the non-imaging pixel, 
 a second pixel having a first source-follower transistor, and 
 an amplifier; 
 
 the non-imaging pixel includes a second source-follower transistor; and 
 the amplifier is configured to generate the reference voltage based at least in part on (a) a first voltage supplied to a gate of the first source-follower transistor and (b) a second voltage supplied to a gate of the second source-follower transistor. 
 
     
     
       13. The imager of  claim 1 , wherein the imager is further configured to generate the offset voltage. 
     
     
       14. A method of operating an imager, the method comprising:
 producing a reference voltage using (a) a nominal reset voltage produced at least in part by a non-imaging pixel of the imager and (b) an offset voltage, 
 determining that the imager is experiencing an eclipsing event, and 
 improving, based at least in part on the determination and the reference voltage, a quality of an image captured by the imager. 
 
     
     
       15. The method of  claim 14 , wherein determining that the imager is experiencing an eclipsing event includes determining that a reset signal voltage produced at least in part by an imaging pixel of the imager is below a threshold voltage. 
     
     
       16. The method of  claim 14 , wherein improving the quality of the image captured by the imager includes adjusting, based at least in part on the reference voltage, a reset signal voltage produced at least in part by an imaging pixel of the imager. 
     
     
       17. The method of  claim 16 , wherein adjusting the reset signal voltage includes pulling the reset signal voltage up to a correction voltage. 
     
     
       18. The method of  claim 17 , further comprising sampling and holing the correction voltage at least while the imaging pixel is outputting the reset signal voltage. 
     
     
       19. The method of  claim 14 , wherein improving the quality of the image captured by the imager includes adjusting an image signal corresponding to an imaging pixel of the imager and to the image such that the image signal does not correspond to a dark pixel in the image at least when bright light is incident upon the imaging pixel. 
     
     
       20. The method of  claim 14 , wherein producing the reference voltage includes generating the reference voltage using an amplifier and based at least in part on (a) a first voltage supplied to a gate of a first source-follower transistor of the non-imaging pixel and (b) a second voltage supplied to a gate of a second source-follower transistor of another pixel of the imager.