Electronic control apparatus

Abstract

An electronic control apparatus includes a first arithmetic processor and a second arithmetic processor that is communicably connected to the first arithmetic processor. The second arithmetic processor includes a controller configured to (i) shift to a rewriting wait state after outputting a request signal that requests a program rewriting to the first arithmetic processor, and (ii) release the rewriting wait state and shift to a program rewriting process after a predetermined wait time that allows the first arithmetic processor to shift to the program rewriting process elapses after outputting the request signal.

What is claimed is: 
     
       1. An electronic control apparatus comprising:
 a first arithmetic processor having a first memory; and 
 a second arithmetic processor having a second memory and that is communicably connected to the first arithmetic processor, wherein 
 the second arithmetic processor includes a controller configured to (i) shift to a rewriting wait state in which the second arithmetic processor waits to perform a program rewriting process to the second memory of the second arithmetic processor after outputting a request signal to the first arithmetic processor that requests the first arithmetic processor to perform the program rewriting process to the first memory of the first arithmetic processor, and (ii) release the rewriting wait state and shift to the program rewriting process to the second memory of the second arithmetic processor after a predetermined wait time elapses from the outputting of the request signal, the predetermined wait time allowing the first arithmetic processor to shift to the program rewriting process to the first memory of the first arithmetic processor. 
 
     
     
       2. The electronic control apparatus according to  claim 1 , wherein
 the controller is further configured to determine the predetermined wait time based on a maximum activation time of the first arithmetic processor. 
 
     
     
       3. A program rewriting control method that is executed in an electronic control apparatus that includes a first arithmetic processor having a first memory and a second arithmetic processor having a second memory and that is communicably connected to the first arithmetic processor, the method comprising the steps of:
 (a) the second arithmetic processor outputting a request signal to the first arithmetic processor that requests the first arithmetic processor to perform a program rewriting process to the first memory of the first arithmetic processor; 
 (b) the second arithmetic processor, after outputting the request signal to the first arithmetic processor, shifting to a rewriting wait state in which the second arithmetic processor waits to perform the program rewriting process to the second memory of the second arithmetic processor; and 
 (c) the second arithmetic processor releasing the rewriting wait state and shifting to the program rewriting process to the second memory of the second arithmetic processor after a predetermined wait time elapses from the outputting of the request signal, the predetermined wait time allowing the first arithmetic processor to shift to the program rewriting process to the first memory of the first arithmetic processor. 
 
     
     
       4. The program rewriting control method according to  claim 3 , wherein the second arithmetic processor determines the predetermined wait time based on a maximum activation time of the first arithmetic processor. 
     
     
       5. The electronic control apparatus according to  claim 1 , wherein the controller discards information received from the first arithmetic processor while the second arithmetic processor is in the rewriting wait state. 
     
     
       6. The program rewriting control method according to  claim 3 , wherein the second arithmetic processor discards information received from the first arithmetic processor while the second arithmetic processor is in the rewriting wait state.