Image sensor and manufacturing method of the same

Abstract

An image sensor includes a first layer including pixels in a pixel array, and a first logic circuit configured to control the pixel array. Each of the pixels include at least one photodiode configured to generate a charge in response to light, and a pixel circuit configured to generate a pixel signal corresponding to the charge. A second layer includes a second logic circuit that is connected to the pixel array and the first logic circuit and is on the first layer. A third layer includes storage elements that are electrically connected to at least one of the pixels or the first logic circuit and an insulating layer on the storage elements. A lower surface of the insulating layer is attached to an upper portion of the first layer, and an upper surface of the insulating layer is attached to a lower portion of the second layer.

What is claimed is: 
     
       1. An image sensor, comprising:
 a first layer comprising pixels in a pixel array, and a first logic circuit configured to control the pixel array, each of the pixels comprising:
 at least one photodiode configured to generate a charge in response to light; and 
 a pixel circuit configured to generate a pixel signal corresponding to the charge; 
 
 a second layer comprising a second logic circuit electrically connected to the pixel array and the first logic circuit, wherein the second layer is on the first layer; and 
 a third layer comprising storage elements electrically connected to at least one of the pixels or the first logic circuit, and further comprising an insulating layer including the storage elements therein, 
 wherein a lower surface of the insulating layer is directly attached to an upper portion of the first layer, and an upper surface of the insulating layer is directly attached to a lower portion of the second layer, and wherein the first layer and the second layer are free of a semiconductor substrate therebetween. 
 
     
     
       2. The image sensor of  claim 1 , wherein the first layer comprises a first semiconductor substrate, the second layer comprises a second semiconductor substrate, and the third layer is free of through silicon vias (TSVs). 
     
     
       3. The image sensor of  claim 1 , wherein the pixel circuit of the each of the pixels is connected to at least one of the storage elements, and
 each of the pixels is connected to a different storage element among the storage elements. 
 
     
     
       4. The image sensor of  claim 3 , wherein the pixels are configured to be simultaneously activated to generate the charges, and the storage elements are configured to be programmed by the pixel signals. 
     
     
       5. The image sensor of  claim 4 , wherein the storage elements are configured to sequentially output the pixel signals to the first logic circuit. 
     
     
       6. The image sensor of  claim 4 , wherein the pixel circuit of the each of the pixels comprises a switch element connected between the at least one of the storage elements and the at least one photodiode. 
     
     
       7. The image sensor of  claim 1 , wherein the storage elements are configured to store first image data, the first logic circuit is configured to generate the first image data by controlling the pixels to be active during a first time, and
 the first logic circuit is configured to generate a resulting image using the first image data, and second image data, acquired by controlling the pixels to be active during a second time different from the first time. 
 
     
     
       8. The image sensor of  claim 1 , wherein the storage elements comprise at least one of a Metal-Insulator-Metal (MIM) capacitor, a charge trap element, a Magnetic Tunnel Junction (MTJ) element, or a germanium (Ge)-antimony (Sb)-tellurium (Te) (GST) element. 
     
     
       9. The image sensor of  claim 1 , wherein the pixels and the storage elements are connected by copper-to-copper (Cu—Cu) bonding at a boundary between the first layer and the third layer. 
     
     
       10. The image sensor of  claim 1 , wherein the upper surface of the insulating layer is attached to the lower portion of the second layer by an adhesive layer that is between the second layer and the third layer. 
     
     
       11. The image sensor of  claim 1 , wherein a second region of the second layer, in which the second logic circuit is disposed, corresponds to a first region of the first layer, in which the pixel array is disposed, and
 the second logic circuit is electrically connected to at least one of the pixels or the storage elements. 
 
     
     
       12. The image sensor of  claim 11 , wherein the second logic circuit and the storage elements are connected by copper-to-copper (Cu—Cu) bonding at a boundary between the second layer and the third layer, and wherein the boundary is located in an upper portion of the pixel array. 
     
     
       13. The image sensor of  claim 11 , wherein the second logic circuit comprises analog-to-digital converters that are connected to the pixels through the storage elements and are configured to convert the pixel signals into digital pixel signals. 
     
     
       14. The image sensor of  claim 13 , wherein the analog-to-digital converters are connected to the pixels, respectively, and are configured to output the digital pixel signals through column lines. 
     
     
       15. The image sensor of  claim 1 , wherein the first layer further comprises metal wirings connected to the pixel circuit of the each of the pixels, and wherein the metal wirings comprise copper (Cu). 
     
     
       16. An image sensor, comprising:
 a pixel array comprising pixels in a first semiconductor substrate, each of the pixels comprising:
 a photodiode configured to generate a charge in response to light; and 
 a pixel circuit configured to generate a pixel voltage based on the charge; 
 
 a first logic circuit comprising first elements in the first semiconductor substrate, wherein the first logic circuit is configured to control the pixels and is in a first insulating layer on the first semiconductor substrate; 
 a second logic circuit comprising second elements in a second semiconductor substrate that is different from the first semiconductor substrate, wherein the second logic circuit is configured to drive the pixel array and the first logic circuit and is in a second insulating layer on the second semiconductor substrate; and 
 capacitors between the first insulating layer and the second insulating layer, wherein the capacitors are in a third insulating layer that is different from the first insulating layer and the second insulating layer, and are connected to at least one of the pixel array or the first logic circuit, 
 wherein a lower surface of the third insulating layer is directly attached to an upper portion of the first insulating layer, and an upper surface of the third insulating layer is directly attached to a lower portion of the second insulating layer, and 
 wherein the first insulating layer and the second insulating layer are free of a semiconductor substrate therebetween. 
 
     
     
       17. The image sensor of  claim 16 , wherein a lower surface of the third insulating layer faces an upper surface of the first insulating layer, and wherein an upper surface of the third insulating layer faces a lower surface of the second insulating layer. 
     
     
       18. The image sensor of  claim 16 , wherein the pixel circuit of each of the pixels comprises:
 a first driving transistor configured to output a first pixel signal based on the charge generated by the photodiode; 
 a switch element connected to an output terminal of the first driving transistor; and 
 a second driving transistor connected to the switch element and configured to output a second pixel signal. 
 
     
     
       19. An image sensor, comprising:
 a first layer comprising a first semiconductor substrate, a pixel array in a first region of the first semiconductor substrate, and a first logic circuit in a second region around the first region and configured to drive the pixel array; 
 a second layer stacked on the first layer in a direction perpendicular to an upper surface of the first semiconductor substrate, the second layer comprising a second semiconductor substrate, and a second logic circuit on the second semiconductor substrate; 
 a third layer between the first layer and the second layer and comprising storage elements and an insulating layer including the storage elements therein, wherein a lower surface of the insulating layer is directly attached to an upper portion of the first layer and an upper surface of the insulating layer is directly attached to a lower portion of the second layer; and 
 logic vias extending through the insulating layer of the third layer and connecting the first logic circuit to the second logic circuit, wherein the logic vias do not extend through a semiconductor material in the third layer. 
 
     
     
       20. The image sensor of  claim 19 , wherein a length of the logic vias is greater than a thickness of the third layer.