Flip chip curved sidewall self-alignment features for substrate and method for manufacturing the self-alignment features

Abstract

Methods and system for flip chip alignment for substrate and leadframe applications are disclosed and may include placing a semiconductor die on bond fingers of a metal leadframe, wherein at least two of the bond fingers comprise one or more recessed self-alignment features. A reflow process may be performed on the semiconductor die and leadframe, thereby melting solder bumps on the semiconductor die such that a solder bump may be pulled into each of the recessed self-alignment features and aligning the solder bumps on the semiconductor die to the bond fingers. The recessed self-alignment features may be formed utilizing a chemical etch process or a stamping process. A surface of the recessed self-alignment features or the bond fingers of the metal leadframe may be roughened. A solder paste may be formed in the recessed self-alignment features prior to placing the semiconductor die on the bond fingers of the metal leadframe.

What is claimed is: 
     
       1. A method of manufacturing an electronic device, the method comprising:
 placing a plurality of bumps of a semiconductor die on a top side of a plurality of bond fingers of a metal leadframe, wherein:
 each of the plurality of bumps comprises a metal pillar and a solder cap, 
 each of at least two of the plurality of bond fingers comprises a curved sidewall recessed self-alignment feature, and 
 each of the curved sidewall recessed self-alignment feature comprises a maximum width at a top end positioned toward the semiconductor die and a minimum width at a bottom end positioned away from the semiconductor die; and 
 
 performing a mass reflow process, thereby melting the solder cap of each of the plurality of bumps, wherein:
 at least one of the plurality of bumps is configured to be pulled into a respective one of the curved sidewall recessed self-alignment feature to align the plurality of bumps to the plurality of bond fingers, and 
 a continuous bond is formed between the at least one of the plurality of bumps and the respective one of the curved sidewall recessed self-alignment feature that entirely laterally surrounds a portion of the at least one of the bumps. 
 
 
     
     
       2. The method of  claim 1 , wherein a width of the bumps prior to said performing the mass reflow process is no greater than the maximum width of the curved sidewall recessed self-alignment feature. 
     
     
       3. The method of  claim 1 , comprising, prior to said performing the mass reflow process:
 forming a solder paste in each of the curved sidewall recessed self-alignment feature, and 
 placing the bumps of the semiconductor die in contact with the formed solder paste. 
 
     
     
       4. The method of  claim 1 , wherein a first volume of a first portion of the at least one of the plurality of bumps within the respective one of the curved sidewall recessed self-alignment feature is less than a second volume of a second portion of the at least one of the plurality of bumps outside of the respective one of the curved sidewall recessed self-alignment feature. 
     
     
       5. The method of  claim 1 , wherein each of the curved sidewall recessed self-alignment feature is configured to compensate for height differences between the plurality of bond fingers. 
     
     
       6. The method of  claim 1 , comprising roughing a surface of at least one of the curved sidewall recessed self-alignment feature. 
     
     
       7. The method of  claim 1 , wherein, in the top-down view, each of the curved sidewall recessed self-alignment feature is elliptical-shaped. 
     
     
       8. The method of  claim 1 , wherein each of the at least two of the plurality of bond fingers comprises a plurality of the curved sidewall recessed self-alignment feature. 
     
     
       9. An electronic device comprising:
 a metal leadframe comprising a plurality of bond fingers, wherein:
 each of at least two of the plurality of bond fingers comprises a curved sidewall recessed self-alignment feature, and 
 each of the curved sidewall recessed self-alignment feature comprises a maximum width at a top end and a minimum width at a bottom end; and 
 
 a semiconductor die bonded to a top side of the metal leadframe and comprising a plurality of bumps, wherein:
 each of the plurality of bumps comprises a metal pillar, 
 each of the plurality of bumps is soldered to a respective one of the curved sidewall recessed self-alignment feature thereby providing a continuous bond that entirely laterally surrounds a portion of each of the plurality of bumps, and 
 a first height of a first portion of each of the plurality of bumps within the respective one of the curved sidewall recessed self-alignment feature is less than a second height of a second portion of each of the plurality of bumps outside of the respective one of the curved sidewall recessed self-alignment feature. 
 
 
     
     
       10. The electronic device of  claim 9 , wherein said each of the plurality of bumps is mass-reflow soldered to the respective one of the curved sidewall recessed self-alignment feature. 
     
     
       11. The electronic device of  claim 9 , wherein the inner surface of at least one of the curved recessed self-alignment feature is roughened. 
     
     
       12. The electronic device of  claim 9 , wherein, in the top-down view, each of the curved sidewall recessed self-alignment feature is elliptical-shaped. 
     
     
       13. The electronic device of  claim 9 , wherein at least one of the plurality of bond fingers comprises a plurality of the curved sidewall recessed self-alignment feature. 
     
     
       14. An electronic device comprising:
 a metal leadframe comprising a plurality of bond fingers, wherein:
 each of at least two of the plurality of bond fingers comprises a curved sidewall recessed self-alignment feature with no flat surfaces, and 
 each of the curved sidewall recessed self-alignment feature is elliptical-shaped in a top-down view; and 
 
 a semiconductor die bonded to a top side of the metal leadframe and comprising a plurality of bumps, wherein:
 each of the plurality of bumps comprises a metal pillar, 
 each of the plurality of bumps is soldered to a respective one of the curved sidewall recessed self-alignment feature thereby providing a continuous bond that entirely laterally surrounds a portion of each of the plurality of bumps, and 
 a first volume of a first portion of each of the plurality of bumps within the respective one of the curved sidewall recessed self-alignment feature is less than a second volume of a second portion of each of the plurality of bumps outside of the respective one of the curved sidewall recessed self-alignment feature. 
 
 
     
     
       15. The electronic device of  claim 14 , wherein said each of the plurality of bumps is mass-reflow soldered to the respective one of the curved sidewall recessed self-alignment feature. 
     
     
       16. The electronic device of  claim 14 , wherein each of the plurality of bumps comprises a maximum width that is no greater than a width of the respective one of the curved sidewall recessed self-alignment feature. 
     
     
       17. The electronic device of  claim 14 , wherein a surface of at least one of the curved recessed self-alignment feature is roughened. 
     
     
       18. The electronic device of  claim 14 , wherein at least one of the plurality of bond fingers comprises a plurality of the curved sidewall recessed self-alignment feature.