Substrate-enhanced comparator and electronic device

Abstract

The present disclosure provides a substrate-enhanced comparator and electronic device, the comparator including: a cross-coupled latch, for connecting input signals to the gate of a cross-coupled MOS transistor to form a first input of the latch; output buffers, connected to the cross-coupled latch for amplifying output signals of the latch; AC couplers, connected to the output buffers for receiving and amplifying the output signals of the latch, coupling the output signals to substrates of the cross-coupled MOS transistors to form second inputs of the latch. The cross-coupled latch is also for output signal regenerative latching based on input signals sampled at the first inputs and input signals sampled at the second inputs. The present disclosure introduces additional substrate inputs to the cross-coupled structure of the conventional latch as the second inputs of the latch.

What is claimed is: 
     
       1. A substrate-enhanced comparator, comprising:
 a cross-coupled latch, comprising cross-coupled Metal-Oxide-Semiconductor (MOS) transistors, wherein the cross-coupled latch connects input signals to gates of the cross-coupled MOS transistors to form first inputs of the cross-coupled latch; 
 output buffers, connected to the cross-coupled latch, for amplifying output signals of the cross-coupled latch; and 
 AC couplers, each connected to one of the output buffers, for receiving and further amplifying the output signals of the cross-coupled latch, and coupling the output signals to substrates of the cross-coupled MOS transistors for forming second inputs of the cross-coupled latch; 
 wherein the cross-coupled latch is further configured for output signal regenerative latching based on input signals sampled at the first inputs and input signals sampled at the second inputs. 
 
     
     
       2. The substrate-enhanced comparator according to  claim 1 , wherein the substrates of the cross-coupled MOS transistors are made by a deep well process. 
     
     
       3. The substrate-enhanced comparator according to  claim 1 , wherein during resetting and latching phases, corresponding output node and input node of the cross-coupled latch are in the same position, which receives signals when the cross-coupled latch is in a sampling phase, and performs positive feedback output signal regeneration when the cross-coupled latch is in the latching phase. 
     
     
       4. The substrate-enhanced comparator according to  claim 1 , wherein the output buffers amplify the output signals of the cross-coupled latch in the same or opposite direction to ensure that cross-coupled MOS transistors on the same side have input signals with the same phase on their substrates, and on their gates. 
     
     
       5. The substrate-enhanced comparator according to  claim 1 , further comprising: substrate common-mode resettors connected to the cross-coupled latch, and AC couplers, respectively, for common-mode resetting of the AC couplers and the substrates of the cross-coupled MOS transistors during a resetting phase. 
     
     
       6. The substrate-enhanced comparator according to  claim 5 , wherein the substrate common-mode resettors reset output nodes of the cross-coupled latch and the substrates of the cross-coupled MOS transistors during a resetting phase, with a corresponding reset voltage connected to different AC couplers for resetting according to respective transconductance of each NMOS transistor and PMOS transistor of the cross-coupled MOS transistors. 
     
     
       7. The substrate-enhanced comparator according to  claim 1 , wherein the cross-coupled latch comprises transistors P 1 , P 2 , P 3 , N 1 , N 2 , N 3 , and N 4 , a gate of the transistor P 1  is connected to a first clock signal, a source of the transistor P 1  is connected to a supply voltage, a drain of the transistor P 1  is connected to sources of the transistors P 2  and P 3  respectively; a first input signal is connected to a first output node formed by connecting a drain of the transistor P 2 , a gate of the transistor P 3 , the first input signal, drains of the transistors N 2 , N 3 , and a gate of the transistor N 4 ; a second input signal is connected to a second output node formed by connecting a gate of the transistor P 2 , a drain of the transistor P 3 , a source of the transistor N 2 , a gate of the transistor N 3  and a drain of the transistor N 4 ; a gate of the transistor N 1  is connected to a second clock signal, a gate of the transistor N 2  is connected to a third clock signal, a drain of the transistor N 2  is connected to sources of the transistors N 3  and N 4  respectively, a source of transistor N 1  is grounded; substrates of the transistor P 2  and the transistor N 3  are interconnected, which are designated as substrates on a first side of the cross-coupled MOS transistors; substrates of the transistor P 3  and the transistor N 4  are interconnected, which are designated as substrates on a second side of the cross-coupled MOS transistors. 
     
     
       8. The substrate-enhanced comparator according to  claim 7 , wherein the output buffers comprise a first output buffer comprising transistors P 4  and N 5  and a second output buffer comprising transistors P 5  and N 6 , in the first output buffer, gates of the transistors P 4  and N 5  are connected to an output of the cross-coupled latch, a source of transistor P 4  is connected to a supply voltage, a source of the transistor N 5  is grounded, drains of the transistors P 4  and N 5  are interconnected as an amplifying output of the first output buffer; in the second output buffer, gates of the transistors P 5  and N 6  are connected to the other output of the cross-coupled latch, a source of the transistor P 5  is connected to a supply voltage, a source of the transistor N 6  is grounded, drains of the transistors P 5  and N 6  are interconnected as an amplifying output of the second output buffer. 
     
     
       9. The substrate-enhanced comparator according to  claim 8 , wherein the AC couplers comprises a first AC coupler comprising a first capacitor and a third capacitor, and a second AC coupler comprising a second capacitor and a fourth capacitor; upper plates of the first capacitor and third capacitor are connected to an output of the first output buffer, and a lower plate of the first capacitor is connected to a first substrate on the first side of the cross-coupled MOS transistors, and a lower plate of the third capacitor is connected to a second substrate on the first side of the cross-coupled MOS transistors; upper plates of the second and fourth capacitors are connected to an output of the second output buffer, a lower plate of the second capacitor is connected to a first substrate on the second side of the cross-coupled MOS transistors, and a lower plate of the fourth capacitor is connected to a second substrate on the second side of the cross-coupled MOS transistors. 
     
     
       10. The substrate-enhanced comparator according to  claim 5 , wherein the substrate common-mode resettors comprise a first substrate common-mode resettor comprising transistors N 7  and N 9  and a second substrate common-mode resettor comprising transistors N 8  and N 10 ; gates of the transistors N 7  and N 9  in the first substrate common-mode resettor are connected to a third clock signal, a drain of the transistor N 7  is connected to an output of the cross-coupled latch, a source of the transistor N 9  is connected to a common mode level, a source of the transistor N 7  and a drain of the transistor N 9  serve as two outputs of the first substrate common mode resettor; gates of the transistors N 8  and N 10  in the second substrate common mode resettor are connected to the third clock signal, a drain of the transistor N 8  is connected to another output of the cross-coupled latch, a source of transistor N 10  is connected to a common mode level, and a source of the transistor N 8 , and a drain of the transistor N 10  serve as two outputs of the second substrate common-mode resettor. 
     
     
       11. The substrate-enhanced comparator according to  claim 10 , wherein the AC couplers comprises a first AC coupler comprising a first capacitor and a third capacitor, and a second AC coupler comprising a second capacitor and a fourth capacitor;
 upper plates of the first capacitor and third capacitor are connected to an output of the first output buffer and a first output of the first substrate common-mode resettor, and a lower plate of the first capacitor is connected to a first substrate on the first side of the cross-coupled MOS transistors and a second output of the first substrate common-mode resettor, and the lower plate of the third capacitor is connected to a second substrate on the first side of the cross-coupled MOS transistors and the second output of the first substrate common-mode resettor; upper plates of the second and fourth capacitors are connected to an output of the second output buffer and a first output of the second substrate common-mode resettor, a lower plate of the second capacitor is connected to a first substrate on the second side of the cross-coupled MOS transistors and a second output of the second substrate common-mode resettor, and a lower plate of the fourth capacitor is connected to a second substrate on the second side of the cross-coupled MOS transistors and the second output of the second substrate common-mode resettor. 
 
     
     
       12. An electronic device comprising the comparator of  claim 1 .