Apparatus for transmitting and receiving a signal, a method of operating the same, a memory device, and a method of operating the memory device

Abstract

A signal transmitting and receiving apparatus including: a first on-die termination circuit connected to a first pin through which a first signal is transmitted or received and, when enabled, the first on-die termination circuit is configured to provide a first termination resistance to a signal line connected to the first pin; a second on-die termination circuit connected to a second pin through which a second signal is transmitted or received and, when enabled, the second on-die termination circuit is configured to provide a second termination resistance to a signal line connected to the second pin; and an on-die termination control circuit configured to independently control an enable time and a disable time of each of the first on-die termination circuit and the second on-die termination circuit.

What is claimed is: 
     
       1. A memory device, comprising:
 a first on-die termination circuit connected to a data pin for transmitting or receiving a data signal and, when enabled, the first on-die termination circuit is configured to provide a first termination resistance to a signal line connected to the data pin; 
 a second on-die termination circuit connected to a read data strobe pin for transmitting or receiving a read data strobe signal and, when enabled, the second on-die termination circuit is configured to provide a second termination resistance to a signal line connected to the read data strobe pin; and 
 an on-die termination control circuit configured to independently control an enable timing and a disable timing of the first on-die termination circuit and an enable timing and a disable timing of the second on-die termination circuit, 
 wherein when a read command is provided from a memory controller, the on-die termination control circuit is configured to control the second on-die termination circuit in an enable state to be disabled after a first time period, control the first on-die termination circuit in an enable state to be disabled after a second time period, control the first on-die termination circuit in the disable state to be enabled after a third time period, and control the second on-die termination circuit in the disable state to be enabled after a fourth time period, 
 wherein the first time period is shorter than the second time period, the second time period is shorter than the third time period, and the third time period is shorter than the fourth time period, and 
 wherein the first time period, the second time period, the third time period, and the fourth time period are determined based on a read latency, respectively. 
 
     
     
       2. The memory device of  claim 1 ,
 wherein the first time period, the second time period, the third time period, and the fourth time period are stored in the memory device. 
 
     
     
       3. The memory device of  claim 1 ,
 wherein the second time period is greater than the first time period by a read data strobe signal preamble time. 
 
     
     
       4. The memory device of  claim 1 ,
 wherein the fourth time period is greater than the third time period by a read data strobe signal postamble time. 
 
     
     
       5. The memory device of  claim 1 ,
 wherein the memory device transmits the data signal to the memory controller before the first on-die termination circuit is enabled after the first on-die termination circuit is disabled, and transmits the read data strobe signal to the memory controller before the second on-die termination circuit is enabled after the second on-die termination circuit is disabled. 
 
     
     
       6. The memory device of  claim 1 ,
 wherein the memory device receives the data signal from outside the memory device through the data pin before the second on-die termination circuit is enabled after the first on-die termination circuit is enabled. 
 
     
     
       7. The memory device of  claim 1 ,
 wherein the memory device provides an indicator signal to the memory controller through a mode register, the indicator signal indicating that the memory device has the ability to independently control the first on-die termination circuit and the second on-die termination circuit. 
 
     
     
       8. A memory device, comprising:
 a first on-die termination circuit connected to a data pin for transmitting or receiving a data signal and, when enabled, the first on-die termination circuit is configured to provide a first termination resistance to a signal line connected to the data pin; 
 a second on-die termination circuit connected to a read data strobe pin for transmitting or receiving a read data strobe signal and, when enabled, the second on-die termination circuit is configured to provide a second termination resistance to a signal line connected to the read data strobe pin; and 
 an on-die termination control circuit configured to simultaneously control the first on-die termination circuit and the second on-die termination circuit to be enabled or disabled when the memory device does not have the ability to independently control the first on-die termination circuit and the second on-die termination circuit, and independently control an enable timing and a disable timing of the first on-die termination circuit and an enable tinting and a disable timing of the second on-die termination circuit when the memory device has the ability to independently control the first on-die termination circuit and the second on-die termination circuit, 
 wherein the memory device provides an indicator signal to a memory controller through a mode register, the indicator signal indicating that the memory device has the ability to independently control the first on-die termination circuit and the second on-die termination circuit. 
 
     
     
       9. The memory device of  claim 8 ,
 wherein when the memory device has the ability to independently control the first on-die termination circuit and the second on-die termination circuit, and a read command is provided from the mentors controller, the on-die termination control circuit configured to control the second on-die termination circuit in an enable state to be disabled after a first time period, control the first on-die termination circuit in an enable state to be disabled after a second time period, control the first on-die termination circuit in the disable state to be enabled after a third time period, and control the second on-die termination circuit in the disable state to be enabled after a fourth time period, 
 wherein the first time period is shorter than the second time period, the second time period is shorter than the third time period, and the third time period is shorter than the fourth time period, and 
 wherein the first time period, the second time period, the third time period, and the fourth time period are determined based on a read latency, respectively. 
 
     
     
       10. The memory device of  claim 9 ,
 wherein the first time period, the second time period, the third time period, and the fourth time period are stored in the memory device. 
 
     
     
       11. The memory device of  claim 9 ,
 wherein the second time period is greater than the first time period by a read data strobe signal preamble time. 
 
     
     
       12. The memory device of  claim 9 ,
 wherein the fourth time period is greater than the third time period by a read data strobe signal postamble time. 
 
     
     
       13. The memory device of  claim 9 ,
 wherein the memory device transmits the data signal to the memory controller before the first on-die termination circuit is enabled after the first on-die termination circuit is disabled, and transmits the read data strobe signal to the memory controller before the second on-die termination circuit is enabled after the second on-die termination circuit is disabled. 
 
     
     
       14. The memory device of  claim 9 ,
 wherein the memory device receives the data signal from outside the memory device through the data pin before the second on-die termination circuit is enabled after the first on-die termination circuit is enabled. 
 
     
     
       15. A memory system, comprising:
 a memory device; and 
 a memory controller configured to control the memory device, 
 wherein the memory device comprises: 
 a first on-die termination circuit connected to a data pin for transmitting or receiving a data signal and, when enabled, the first on-die termination circuit is configured to provide a first termination resistance to a signal line connected to the data pin; 
 a second on-die termination circuit connected to a read data strobe pin for transmitting or receiving a read data strobe signal and, when enabled, the second on-die termination circuit is configured to provide a second termination resistance to a signal line connected to the read data strobe pin; and 
 an on-die termination control circuit configured to simultaneously control the first on-die termination circuit and the second on-die termination circuit to be enabled or disabled when the memory device does not have the ability to independently control the first on-die termination circuit and the second on-die termination circuit, and independently control an enable timing and a disable timing of the first on-die termination circuit and an enable timing and a disable timing of the second on-die termination circuit when the memory device has the ability to independently control the first on-die termination circuit and the second on-die termination circuit, 
 wherein the memory controller is configured to read a mode register to obtain an indicator signal; 
 wherein the indicator signal indicates that the memory device has the ability to independently control the first on-die termination circuit and the second on-die termination circuit. 
 
     
     
       16. The memory system of  claim 15 ,
 wherein when the memory device has the ability to independently control the first on-die termination circuit and the second on-die termination circuit, and a read command is provided from the memory controller, the on-die termination control circuit is configured to control the second on-die termination circuit in an enable state to be disabled after a first time period, control the first on-die termination circuit in an enable state to be disabled after a second time period, control the first on-die termination circuit in the disable state to be enabled after a third time period, and control the second on-die termination circuit in the disable state to be enabled after a fourth time period, 
 wherein the first time period is shorter than the second time period, the second time period is shorter than the third time period, and the third time period is shorter than the fourth time period, and 
 wherein the first time period, the second time period, the third time period, and the fourth time period are determined based on a read latency, respectively. 
 
     
     
       17. The memory system of  claim 16 ,
 wherein the first time period, the second time period, the third time period, and the fourth time period are stored in the memory device. 
 
     
     
       18. The memory system of  claim 16 ,
 wherein the second time period is greater than the first time period by a read data strobe signal preamble time, 
 wherein the fourth time period is greater than the third time period by a read data strobe signal postamble time. 
 
     
     
       19. The memory system of  claim 16 ,
 wherein the memory device transmits the data signal to the memory controller before the first on-die termination circuit is enabled after the first on-die termination circuit is disabled, and transmits the read data strobe signal to the memory controller before the second on-die termination circuit is enabled after the second on-die termination circuit is disabled. 
 
     
     
       20. The memory system of  claim 16 ,
 wherein the memory device receives the data signal from outside the memory device through the data pin before the second on-die termination circuit is enabled after the first on-die termination circuit is enabled.