Systems and methods for fast layered decoding for low-density parity-check (LDPC) codes

Abstract

According to certain embodiments, a method is provided for fast layered decoding for Low-density Parity-Check (LDPC) codes with a Parity-Check Matrix (PCM) that includes at least a first layer and a second layer. The method includes reading, from a memory, Variable Node (VN) soft information, wherein the VN soft information is associated with a message from a VN to a Check Node (CN) of the second layer of the PCM. A new CN to VN message is calculated from the CN of the second layer of the PCM. New VN soft information is calculated for the VN. The new VN soft information is calculated based on the VN soft information and a new CN to VN message from a CN of the first layer to the VN and an old CN to VN message from the CN of the first layer to the VN such that the updating of new VN soft information is delayed by at least one layer. The fast layered decoding has lower decoding latency and utilizes the decoding hardware more efficiently than standard layered decoding techniques. This may be achieved by keeping the memory access and processing hardware units active simultaneously to avoid excess decoding latency. More specifically, certain embodiments may carry out memory access and computation process simultaneously, without any effort to make the row layers mutually orthogonal to each other. Another technical advantage may be that the proposed decoding algorithm adjusts the LLRs to partially account for deviations from the layered decoding due to non-orthogonal rows.

The invention claimed is: 
     
       1. A method for fast layered decoding for Low-density Parity-Check (LDPC) codes with a Parity-Check Matrix (PCM) comprising at least a first layer and a second layer, the method comprising:
 reading, from a memory, Variable Node (VN) soft information, wherein the VN soft information is associated with a message from a VN to a Check Node (CN) of the second layer of the PCM; 
 calculating a new CN to VN message from the CN of the second layer of the PCM; and 
 calculating new VN soft information for the VN, wherein the new VN soft information is calculated based on the VN soft information and a new CN to VN message from a CN of the first layer to the VN and an old CN to VN message from the CN of the first layer to the VN such that the updating of the new VN soft information is delayed by at least one layer, and wherein calculating the new VN soft information comprises adjusting the VN soft information to partially account for deviations from the layered decoding due to non-orthogonal rows; 
 determining a correlation between all pairs of layers; and 
 based on the correlation, reordering at least two of the layers. 
 
     
     
       2. The method of  claim 1 , further comprising switching from delayed updating to real-time updating of the VN soft information. 
     
     
       3. The method of  claim 1 , wherein at least one of the VN soft information and the new VN soft information comprises a log-likelihood ratio (LLR) value. 
     
     
       4. The method of  claim 1 , wherein while processing circuitry is calculating the new soft information for the VN, the method further includes simultaneously accessing the memory and performing at least one of:
 reading soft information of a VN associated with the CN from the memory; 
 reading a message from the CN in the first layer from the memory; 
 writing soft information of the VN in the first layer to the memory; and 
 writing soft information associated with a message from the CN in the first layer to the VN. 
 
     
     
       5. The method of  claim 1 , wherein at least one of the soft information for the VN associated with the CN in the first layer may be based on an old message from the CN associated with the VN and a new message from the CN associated with the VN. 
     
     
       6. The method of  claim 1 , wherein the method is performed by a wireless device. 
     
     
       7. The method of  claim 1 , wherein the method is performed by a network node. 
     
     
       8. A system for fast layered decoding for Low-Density Parity-Check (LDPC) codes defined with a parity check matrix (PCM) comprising a first layer and a second layer, the system comprising:
 a memory storing instructions; and 
 processing circuitry operable to execute the instructions to cause the processing circuitry to: 
 obtain Variable node (VN) soft information associated with a message from a VN to a Check Node (CN) of the second layer of the PCM; and 
 calculate a new CN to VN message from the CN of the second layer of the PCM; and 
 calculate new VN soft information for the VN, wherein the new VN soft information is calculated based on the VN soft information and a new CN to VN message from a CN of the first layer to the VN and an old CN to VN message from the CN of the first layer to the VN such that the updating of the new VN soft information is delayed by at least one layer, and wherein calculating the new VN soft information comprises adjusting the VN soft information to partially account for deviations from the layered decoding due to non-orthogonal rows; 
 determine a correlation between all pairs of layers; and 
 based on the correlation, reorder at least two of the layers. 
 
     
     
       9. The system of  claim 8 , wherein the processing circuitry is further operable to execute the instructions to cause the processing circuitry to switch from delayed updating to real-time updating of the VN soft information. 
     
     
       10. The system of  claim 8 , wherein at least one of the VN soft information and the new VN soft information comprises a log-likelihood ratio (LLR) value. 
     
     
       11. The system of  claim 10 , wherein the message from the VN to the CN of the second layer is the difference between the VN soft information and an old CN to VN message from the CN of the second layer to the VN. 
     
     
       12. The system of  claim 8 , wherein while the processing circuitry is calculating the new soft information for the VN, the memory is simultaneously accessed and at least one of the following operations is performed:
 reading soft information of a VN associated with a CN from the memory; 
 reading a message from the CN in the first layer from the memory; 
 writing soft information of the VN to the memory; and 
 writing soft information associated with a message from the CN in the first layer to the VN. 
 
     
     
       13. The system of  claim 8 , wherein the VN soft information for the VN associated with the CN in the first layer may be based on an old message from the CN associated with the VN and a new message from the CN associated with the VN. 
     
     
       14. The system of  claim 8 , wherein the new CN to VN message is calculated as a function of a set of values associated with a plurality of messages from a plurality of VNs to the CN of the second layer of the PCM. 
     
     
       15. The system of  claim 8 , wherein the correlation may be defined as the inner product of blocks in layers, where each block will map to 0 if its value is −1 and to 1, otherwise. 
     
     
       16. The system of  claim 8 , wherein the message from the VN to the CN of the second layer is a function of the VN soft information and an old CN to VN message from the CN of the second layer to the VN. 
     
     
       17. The system of  claim 8 , wherein the system comprises a wireless device. 
     
     
       18. The system of  claim 8 , wherein the system comprises a network node.