P
US11665443B2ActiveUtilityPatentIndex 69

Image sensor

Assignee: SAMSUNG ELECTRONICS CO LTDPriority: Feb 22, 2021Filed: Feb 17, 2022Granted: May 30, 2023
Est. expiryFeb 22, 2041(~14.6 yrs left)· nominal 20-yr term from priority
Inventors:OH YOUNGSUNBAE HYUNGJINLIM MOOSUP
H04N 25/771H04N 25/78H04N 25/62H04N 25/616H04N 25/76H04N 25/585H04N 25/59H04N 25/77H04N 25/70H04N 25/766H04N 25/75
69
PatentIndex Score
2
Cited by
17
References
20
Claims

Abstract

An image sensor including a pixel that includes: a first photodiode; a second photodiode having a larger light-receiving area than the first photodiode; a first floating diffusion node accumulating charges of the first photodiode; a second floating diffusion node accumulating charges of the second photodiode; a capacitor accumulating charges overflowing from the first photodiode; a first switch transistor having a first end connected to the first floating diffusion node and a second end connected to the capacitor; and a driving transistor configured to convert the accumulated charges into a pixel signal, the first switch transistor is turned on in a low conversion gain (LCG) mode of a readout section of the first photodiode, and is turned off in a high conversion gain (HCG) mode of the readout section of the first photodiode, and the readout circuit generates image data based on pixel signals from the first and second sections.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
       1. An image sensor comprising a pixel array in which a plurality of pixels are arranged and a readout circuit,
 wherein at least one of the plurality of pixels comprises: 
 a first photodiode; 
 a second photodiode having a larger light-receiving area than the first photodiode; 
 a first floating diffusion node in which charges generated by the first photodiode accumulate; 
 a second floating diffusion node in which charges generated by the second photodiode accumulate; 
 a first capacitor configured to accumulate charges that overflow from the first photodiode; 
 a first switch transistor having a first end connected to the first floating diffusion node and a second end connected to the first capacitor, and 
 a driving transistor configured to convert the charges accumulated in the first floating diffusion node and the second floating diffusion node into a pixel signal, 
 wherein the first switch transistor is turned on in a first section operating in a low conversion gain (LCG) mode of a readout section of the first photodiode, and 
 is turned off in a second section operating in a high conversion gain (HCG) mode of the readout section of the first photodiode, and 
 wherein the readout circuit generates image data based on first pixel signals read out from the first section and second pixel signals read out from the second section. 
 
     
     
       2. The image sensor of  claim 1 , wherein the first pixel signals correspond to a first luminance range,
 wherein the second pixel signals correspond to a second luminance range that is at least partially equal to or less than the first luminance range. 
 
     
     
       3. The image sensor of  claim 1 , wherein the at least one pixel comprises:
 a reset transistor having a first end connected to the first floating diffusion node and a second end to which a reset voltage is applied; and 
 a first transmission transistor having a first end connected to the first photodiode and a second end connected to the first floating diffusion node. 
 
     
     
       4. The image sensor of  claim 3 , wherein the image sensor outputs a voltage corresponding to an amount of the charges overflowed from the first photodiode and accumulated in the first capacitor, as a first image signal, in the first section,
 turns on the reset transistor after outputting the first image signal to reset the first capacitor and the first floating diffusion node, and 
 turns off the reset transistor after the reset, and outputs a voltage corresponding to an amount of charges accumulated in the first capacitor after the first capacitor has been reset as a first reset signal. 
 
     
     
       5. The image sensor of  claim 4 , wherein the image sensor turns off the first switch transistor after outputting the first reset signal,
 outputs a voltage corresponding to the first floating diffusion node that has been reset as a second reset signal in the second section, and 
 turns on the first transmission transistor after outputting the reset signal, accumulates charges generated by the first photodiode in the first floating diffusion node, and outputs a voltage corresponding to the accumulated charge amount in the first floating diffusion node as a second image signal. 
 
     
     
       6. The image sensor of  claim 3 , wherein at least one of the plurality of pixels comprises:
 a second transmission transistor having a first end connected to the second photodiode and a second end connected to the second floating diffusion node; and 
 a conversion gain transistor having a first end connected to the first floating diffusion node and a second end connected to the second floating diffusion node. 
 
     
     
       7. The image sensor of  claim 6 , wherein the conversion gain transistor is turned on in a third section operating in the low conversion gain (LCG) mode of a readout section of the second photodiode, and
 is turned off in a fourth section operating in the high conversion gain (HCG) mode of the readout section of the second photodiode, 
 wherein the readout circuit generates image data based on third pixel signals read out from the third section and fourth pixel signals read out from the fourth section. 
 
     
     
       8. The image sensor of  claim 7 , wherein the first pixel signals correspond to a first luminance range,
 wherein the second pixel signals correspond to a second luminance range that is at least partially equal to or less than the first luminance range, 
 wherein the third pixel signals correspond to a third luminance range that is at least partially equal to or less than the second luminance range, 
 wherein the fourth pixel signals correspond to a fourth luminance range that is at least partially equal to or less than the third luminance range. 
 
     
     
       9. The image sensor of  claim 1 , wherein at least one of the plurality of pixels comprises:
 a second switch transistor having a first end connected to a node in which the first switch transistor and the first capacitor are connected to each other; and 
 a second capacitor connected to a second end of the second switch transistor. 
 
     
     
       10. The image sensor of  claim 9 , wherein the second switch transistor is turned on in a first section operating in the low conversion gain (LCG) mode of a readout section of the first photodiode, and
 is turned off in a second section operating in the high conversion gain (HCG) mode of the readout section of the first photodiode. 
 
     
     
       11. An image sensor comprising a pixel array in which a plurality of pixels are arranged and a readout circuit, wherein at least one of the plurality of pixels comprises:
 a first photodiode; 
 a second photodiode having a larger light-receiving area than the first photodiode; 
 a first transmission transistor configured to transmit charges generated by the first photodiode; 
 a second transmission transistor configured to transmit charges generated by the second photodiode; 
 a first floating diffusion node in which charges transmitted through the first transmission transistor accumulate; 
 a second floating diffusion node in which charges transmitted through the second transmission transistor accumulate; 
 a gain control transistor having a first end connected to the first floating diffusion node and a second end connected to the second floating diffusion node; 
 a first capacitor configured to accumulate charges that overflow from the first photodiode; 
 a first switch transistor having a first end connected to the first floating diffusion node and a second end connected to the first capacitor; 
 a reset transistor having a first end connected to the first floating diffusion node and a second end to which a reset voltage is applied; and 
 a driving transistor configured to convert charges accumulated in the first floating diffusion node and the second floating diffusion node into a pixel signal. 
 
     
     
       12. The image sensor of  claim 11 , wherein the first switch transistor is turned on in a first section operating in a low conversion gain (LCG) mode of a readout section of the first photodiode, and
 is turned off in a second section operating in a high conversion gain (HCG) mode of the readout section of the first photodiode. 
 
     
     
       13. The image sensor of  claim 12 , wherein the gain control transistor is turned on in a third section operating in the low conversion gain (LCG) mode of a readout section of the second photodiode, and
 is turned off in a fourth section operating in the high conversion gain (HCG) mode of the readout section of the second photodiode. 
 
     
     
       14. The image sensor of  claim 13 , wherein the readout circuit generates image data based on first pixel signals read out from the first section, second pixel signals read out from the second section, third pixel signals read out from the third section, and fourth pixel signals read out from the fourth section. 
     
     
       15. The image sensor of  claim 14 , wherein the first pixel signals correspond to a first luminance range,
 wherein the second pixel signals correspond to a second luminance range that is at least partially equal to or less than the first luminance range, 
 wherein the third pixel signals correspond to a third luminance range that is at least partially equal to or less than the second luminance range, 
 wherein the fourth pixel signals correspond to a fourth luminance range that is at least partially equal to or less than the third luminance range. 
 
     
     
       16. The image sensor of  claim 11 , wherein at least one of the plurality of pixels comprises:
 a second switch transistor having a first end connected to a node in which the first switch transistor and the first capacitor are connected to each other; and 
 a second capacitor connected to a second end of the second switch transistor. 
 
     
     
       17. The image sensor of  claim 16 , wherein the second switch transistor is turned on in a first section operating in a low conversion gain (LCG) mode of a readout section of the first photodiode, and
 is turned off in a second section operating in a high conversion gain (HCG) mode of the readout section of the first photodiode. 
 
     
     
       18. An image sensor comprising a pixel array in which a plurality of pixels are arranged and a readout circuit, wherein at least one of the plurality of pixels comprises:
 a first photodiode; 
 a second photodiode having a larger light-receiving area than the first photodiode; 
 a first floating diffusion node in which charges generated by the first photodiode accumulate; 
 a first capacitor configured to accumulate charges that overflow from the first photodiode; 
 a first switch transistor having a first end connected to the first floating diffusion node and a second end connected to the first capacitor; 
 a second switch transistor connected to the first floating diffusion node; 
 a second floating diffusion node in which charges transmitted through the switch transistor accumulate; and 
 a driving transistor configured to convert the charges accumulated in the second floating diffusion node into a pixel signal. 
 
     
     
       19. The image sensor of  claim 18 , wherein the first switch transistor is turned on in a first section operating in a low conversion gain (LCG) mode of a readout section of the first photodiode, and
 is turned off in a second section operating in a high conversion gain (HCG) mode of the readout section of the first photodiode. 
 
     
     
       20. The image sensor of  claim 18 , wherein the second switch transistor is turned on in the readout section of the first photodiode, and
 is turned off in a readout section of the second photodiode.

Cited by (0)

No later patents cite this yet.

References (0)

No backward citations on record.