Technologies for high-precision timestamping of packets

Abstract

Technologies for high-precision timestamping of data packets is disclosed. Several sources of errors that may arise when timestamping the arrival or sending of data packets may be determined and corrected, including variable latencies, semi-static latencies, and fixed latencies. In the illustrative embodiment, a variable latency may arise due to a phase difference between a clock of a network interface card and a system clock. When a trigger pattern is detected, such as the start of a data packet, a trigger may be sent from a circuit synchronized to the clock of the network interface card to a circuit synchronized to the system clock. The phase difference between the edge of the clock on the network interface card and the edge of the clock of the system clock leads to an error in the timestamp value. Determining the phase difference allows for the error in the timestamp value to be corrected.

What is claimed is: 
     
       1. An apparatus for use in association with a data transmission clock signal, a data reception clock signal, and another clock signal, the apparatus comprising:
 time counter circuitry to generate time count data for use in association with receive data timestamping and send data timestamping, the receive data timestamping being associated with data reception that is based upon the data reception clock signal, the send data timestamping being associated with data transmission that is based upon the data transmission clock signal; 
 latency determination circuitry for use in determining, at least in part, signal propagation-related latency data; and 
 phase difference determining circuitry for use in determining, at least in part, phase difference data, the phase difference data being based upon phase of the another clock signal relative to at least one phase of the data transmission clock signal and/or the data reception clock signal; 
 wherein:
 the signal propagation-related latency data and the phase difference data are for use in adjusting the time count data so as to compensate, at least in part, for at least one potential synchronization difference related to signal propagation latency and/or clock phase difference. 
 
 
     
     
       2. The apparatus of  claim 1 , wherein:
 the phase difference data is based upon the phase of the another clock signal relative to phases of the data transmission clock signal and the data reception clock signal. 
 
     
     
       3. The apparatus of  claim 2 , wherein:
 the receive data timestamping and the send data timestamping are associated with respective data received and to be transmitted via a network. 
 
     
     
       4. The apparatus of  claim 3 , wherein:
 the apparatus is comprised, at least in part, in field programmable gate array (FPGA) circuitry, application specific integrated circuitry (ASIC), and/or system-on-a-chip (SoC) circuitry. 
 
     
     
       5. At least one non-transitory machine-readable storage medium storing instructions for being executed by at least one machine, the at least one machine being for use in association with a data transmission clock signal, a data reception clock signal, and another clock signal, the instructions, when executed, by the at least one machine resulting in the at least one machine being configured for performance of operations comprising:
 generating, by time counter circuitry of the at least one machine, time count data for use in association with receive data timestamping and send data timestamping, the receive data timestamping being associated with data reception that is based upon the data reception clock signal, the send data timestamping being associated with data transmission that is based upon the data transmission clock signal; 
 determining, at least in part, by latency determination circuitry of the at least one machine, signal propagation-related latency data; and 
 determining, at least in part, by phase difference determining circuitry of the at least one machine, phase difference data, the phase difference data being based upon phase of the another clock signal relative to at least one phase of the data transmission clock signal and/or the data reception clock signal; 
 wherein:
 the signal propagation-related latency data and the phase difference data are for use in adjusting the time count data so as to compensate, at least in part, for at least one potential synchronization difference related to signal propagation latency and/or clock phase difference. 
 
 
     
     
       6. The at least one non-transitory machine-readable storage medium of  claim 5 , wherein:
 the phase difference data is based upon the phase of the another clock signal relative to phases of the data transmission clock signal and the data reception clock signal. 
 
     
     
       7. The at least one non-transitory machine-readable storage medium of  claim 6 , wherein:
 the receive data timestamping and the send data timestamping are associated with respective data received and to be transmitted via a network. 
 
     
     
       8. The at least one non-transitory machine-readable storage medium of  claim 7 , wherein:
 the at least one machine is comprised, at least in part, in field programmable gate array (FPGA) circuitry, application specific integrated circuitry (ASIC), and/or system-on-a-chip (SoC) circuitry. 
 
     
     
       9. A method implemented using at least one machine, the at least one machine being for use in association with a data transmission clock signal, a data reception clock signal, and another clock signal, the method comprising:
 generating, by time counter circuitry of the at least one machine, time count data for use in association with receive data timestamping and send data timestamping, the receive data timestamping being associated with data reception that is based upon the data reception clock signal, the send data timestamping being associated with data transmission that is based upon the data transmission clock signal; 
 determining, at least in part, by latency determination circuitry of the at least one machine, signal propagation-related latency data; and 
 determining, at least in part, by phase difference determining circuitry of the at least one machine, phase difference data, the phase difference data being based upon phase of the another clock signal relative to at least one phase of the data transmission clock signal and/or the data reception clock signal; 
 wherein:
 the signal propagation-related latency data and the phase difference data are for use in adjusting the time count data so as to compensate, at least in part, for at least one potential synchronization difference related to signal propagation latency and/or clock phase difference. 
 
 
     
     
       10. The method of  claim 9 , wherein:
 the phase difference data is based upon the phase of the another clock signal relative to phases of the data transmission clock signal and the data reception clock signal. 
 
     
     
       11. The method of  claim 10 , wherein:
 the receive data timestamping and the send data timestamping are associated with respective data received and to be transmitted via a network. 
 
     
     
       12. The method of  claim 11 , wherein:
 the at least one machine is comprised, at least in part, in field programmable gate array (FPGA) circuitry, application specific integrated circuitry (ASIC), and/or system-on-a-chip (SoC) circuitry. 
 
     
     
       13. A computer system for use in association with a data transmission clock signal, a data reception clock signal, and another clock signal, the computer comprising:
 a multi-core processor; 
 solid-state data storage storing instructions for being executed by the multi-core processor; and 
 a network interface card circuitry comprising:
 time counter circuitry to generate time count data for use in association with receive data timestamping and send data timestamping, the receive data timestamping being associated with data reception that is based upon the data reception clock signal, the send data timestamping being associated with data transmission that is based upon the data transmission clock signal; 
 latency determination circuitry for use in determining, at least in part, signal propagation-related latency data; and 
 phase difference determining circuitry for use in determining, at least in part, phase difference data, the phase difference data being based upon phase of the another clock signal relative to at least one phase of the data transmission clock signal and/or the data reception clock signal; 
 
 wherein:
 the signal propagation-related latency data and the phase difference data are for use in adjusting the time count data so as to compensate, at least in part, for at least one potential synchronization difference related to signal propagation latency and/or clock phase difference. 
 
 
     
     
       14. The computer system of  claim 13 , wherein:
 the phase difference data is based upon the phase of the another clock signal relative to phases of the data transmission clock signal and the data reception clock signal. 
 
     
     
       15. The computer system of  claim 14 , wherein:
 the receive data timestamping and the send data timestamping are associated with respective data received and to be transmitted via a network. 
 
     
     
       16. The computer system of  claim 15 , wherein:
 the network interface card circuitry is comprised, at least in part, in field programmable gate array (FPGA) circuitry, application specific integrated circuitry (ASIC), and/or system-on-a-chip (SoC) circuitry.