Memory device

Abstract

A memory device includes a voltage generator that provides a read voltage to a selected word line and provides a pass voltage to a plurality of unselected word lines, and a deterioration level detection circuit. The selected word line and the unselected word lines are connected to a plurality of memory cells. The deterioration level detection circuit detects a deterioration level of memory cells connected to the selected word line based on data of memory cells that receive the read voltage. The memory cells connected to the selected word line and the memory cells that receive the read voltage are included in the plurality of memory cells. The voltage generator changes the pass voltage provided to the unselected word lines based on the deterioration level.

What is claimed is: 
     
       1. A memory device, comprising:
 a memory cell array comprising a plurality of pages, wherein each of the pages comprises a plurality of memory cells; 
 a pass voltage changing circuit that changes a pass voltage supplied to pages connected to unselected word lines based on a degradation level of memory cells included in a page connected to a selected word line, 
 wherein the pages connected to the unselected word lines and the page connected to the selected word line are included in the plurality of pages, 
 wherein the pass voltage changing circuit provides the pass voltage having been changed to at least one page from among the pages connected to the unselected word lines; and 
 a voltage generator that provides a read voltage to the selected word line and provides a pass voltage to the unselected word lines, 
 wherein the voltage generator provides a first pass voltage to the unselected word lines during a first time period for reading a first bit of data stored in a selected memory cell connected to the selected word line, and provides a second pass voltage different from the first pass voltage to the unselected word lines during a second time period for reading a second bit of data stored in the selected memory cell. 
 
     
     
       2. The memory device of  claim 1 , wherein the pass voltage changing circuit provides the pass voltage having been changed to at least one page in which a read operation is completed,
 wherein the at least one page in which the read operation is completed is included in the pages connected to the unselected word lines. 
 
     
     
       3. The memory device of  claim 2 , wherein the at least one page that receives the pass voltage having been changed is disposed on a side based on the selected word line. 
     
     
       4. The memory device of  claim 3 , wherein the pass voltage is received by a plurality of pages, the pages that receive the pass voltage are sequentially disposed, and the read operation is performed in an arrangement direction of the sequentially disposed pages. 
     
     
       5. The memory device of  claim 1 , wherein the pass voltage changing circuit provides the pass voltage having been changed to all of the pages connected to the unselected word lines. 
     
     
       6. The memory device of  claim 1 , wherein the pass voltage changing circuit provides the pass voltage having been changed to pages disposed adjacent to the page connected to the selected word line, wherein the pages disposed adjacent to the page connected to the selected word line are included in the unselected word lines. 
     
     
       7. The memory device of  claim 1 , wherein the degradation level is provided by a memory controller that communicates with the memory device. 
     
     
       8. The memory device of  claim 1 , wherein the first pass voltage includes a prior pass voltage provided to the unselected word lines at a first time point of the first time period and a posterior pass voltage provided to the unselected word lines at a second time point after the first time point,
 wherein the prior pass voltage and the posterior pass voltage have different magnitudes. 
 
     
     
       9. The memory device of  claim 1 , wherein the first pass voltage is determined according to the degradation level detected from a dummy voltage provided prior to the read voltage,
 wherein the second pass voltage is determined according to the degradation level detected from a read voltage during the first time period. 
 
     
     
       10. The memory device of  claim 9 , wherein the voltage generator is configured to provide a third pass voltage varied according to the degradation level detected during the second time period to the unselected word lines during a third time period in which a third bit of the selected memory cell is read. 
     
     
       11. A memory device, comprising:
 a memory cell region including a first metal pad; 
 a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad; 
 a memory cell array in the memory cell region including a plurality of pages, wherein each of the pages comprises a plurality of memory cells; 
 a voltage generator in the peripheral circuit region that provides a read voltage to a selected word line and provides a pass voltage to a plurality of unselected word lines, wherein the selected word line and the unselected word lines are connected to a plurality of memory cells; and 
 a degradation level detection circuit in the peripheral circuit region that detects a degradation level of memory cells connected to the selected word line based on data of memory cells that receive the read voltage, wherein the memory cells connected to the selected word line and the memory cells that receive the read voltage are included in the plurality of memory cells. 
 
     
     
       12. The memory device of  claim 11 , further comprising:
 a dummy voltage supply unit in the peripheral circuit region that provides a dummy voltage to the selected word line before the read voltage is provided to the selected word line, wherein the degradation level detection circuit detects a degradation level of memory cells connected to the selected word line based on data of memory cells that receive the dummy voltage; and 
 a pass voltage changing circuit in the peripheral circuit region that changes the pass voltage provided to the unselected word lines based on the degradation level.