Address translation in a data processing apparatus

Abstract

An apparatus comprises address translation circuitry (70) to perform a translation of a virtual address (80) comprising a virtual tag portion (88) and a virtual address portion (86) into a physical address (82) comprising a physical tag portion (92) and a physical address portion (90). The address translation circuitry comprises address tag translation circuitry (72) to perform a translation of the virtual tag portion into the physical tag portion and the address translation to be performed is selected in dependence on the virtual address.

The invention claimed is: 
     
       1. An apparatus comprising:
 address translation circuitry configured to perform a translation of a virtual address comprising a virtual tag portion and a virtual address portion into a physical address comprising a physical tag portion and a physical address portion, the physical address portion identifying a memory location to which access is required and the physical tag portion indicating whether to perform a predetermined memory operation, and the address translation circuitry comprising: 
 address tag translation circuitry configured to perform a translation of the virtual tag portion into the physical tag portion, 
 wherein the address translation circuitry is configured to select the translation to be performed by the address tag translation circuitry in dependence on the virtual address portion, and 
 wherein the virtual tag portion and the virtual address portion are non-overlapping portions of the virtual address, and the physical tag portion and the physical address portion are non-overlapping portions of the physical address; and 
 a memory system configured to receive the physical address and to access the memory location identified by the physical address portion, wherein the memory system is responsive to reception of the physical address, when a predetermined part of the physical tag portion has a predetermined value, to perform the predetermined memory operation, 
 wherein the predetermined memory operation is a guard tag comparison of the physical tag portion against a guard tag value associated with the memory location and the memory system is responsive to the physical tag portion and the guard tag value not satisfying a match condition to indicate a fault condition. 
 
     
     
       2. The apparatus as claimed in  claim 1 , wherein the translation performed by the address tag translation circuitry is dependent on a most-significant bit of the virtual address portion. 
     
     
       3. The apparatus as claimed in  claim 2 , wherein when the most-significant bit of the virtual address portion has a first value, the selected translation performed by the address tag translation circuitry is configured to generate the physical tag portion matching the virtual tag portion,
 and wherein when the most-significant bit has a second value, the selected translation performed by the address tag translation circuitry is configured to modify the virtual tag portion to generate the physical tag portion. 
 
     
     
       4. The apparatus as claimed in  claim 2 , wherein the apparatus is arranged to allocate virtual addresses for exclusive use by one of kernel-owned processes and user-owned processes, and a value of the most-significant bit of the virtual address portion is indicative of whether the virtual address has been allocated to kernel-owned processes or to user-owned processes. 
     
     
       5. The apparatus as claimed in  claim 1 , wherein the selected translation configured to be performed by the address tag translation circuitry comprises inverting at least a portion of the virtual tag portion to generate the physical tag portion. 
     
     
       6. The apparatus as claimed in  claim 1 , wherein the selected translation configured to be performed by the address tag translation circuitry comprises incrementing at least a portion of the virtual tag portion to generate the physical tag portion. 
     
     
       7. The apparatus as claimed in  claim 1 , wherein when a predetermined part of the physical tag portion has a predetermined value, the match condition is a match-all condition such that any guard tag value will satisfy the match condition. 
     
     
       8. The apparatus as claimed in  claim 7 , wherein when the predetermined part of the physical tag portion does not have the predetermined value the match condition is a match-one condition such that the predetermined part of the physical tag portion and the guard tag value must be the same to satisfy the match condition. 
     
     
       9. The apparatus as claimed in  claim 7 , wherein the predetermined part of the physical tag portion is a predetermined set of bits of the physical tag portion. 
     
     
       10. The apparatus as claimed in  claim 7 , wherein the address tag translation circuitry is responsive to a predetermined bit of the virtual tag portion having a predetermined value to generate the physical tag portion with the predetermined part of the physical tag portion having the predetermined value irrespective of values of other predetermined bits of the virtual tag portion. 
     
     
       11. The apparatus as claimed in  claim 7 , wherein the predetermined part of the physical tag portion is a predetermined bit of the physical tag portion. 
     
     
       12. The apparatus as claimed in  claim 1 , wherein the guard tag comparison is of less than all of the physical tag portion against the guard tag value associated with the memory location. 
     
     
       13. The apparatus as claimed in  claim 7 , wherein the predetermined value of the predetermined part of the physical tag portion has all bits of a same bit-value. 
     
     
       14. The apparatus as claimed in  claim 1 , wherein the virtual tag portion comprises at least one bit which is included in the physical address and the memory system is responsive to the at least one bit to control overwriting of the guard tag associated with the memory location when a write access is made to the memory location. 
     
     
       15. A method comprising:
 selecting a translation to be performed on a virtual address comprising a virtual tag portion and a virtual address portion into a physical address comprising a physical tag portion and a physical address portion, wherein the selecting of the translation is dependent on the virtual address portion, the physical address portion identifying a memory location to which access is required and the physical tag portion indicating whether to perform a predetermined memory operation; and 
 performing the translation to translate the virtual tag portion into the physical tag portion, 
 wherein the virtual tag portion and the virtual address portion are non-overlapping portions of the virtual address, and the physical tag portion and the physical address portion are non-overlapping portions of the physical address; and 
 receiving the physical address and accessing the memory location identified by the physical address portion, and in response to reception of the physical address and a predetermined part of the physical tag portion having a predetermined value, performing the predetermined memory operation, 
 wherein the predetermined memory operation is a guard tag comparison of the physical tag portion against a guard tag value associated with the memory location and the memory system is responsive to the physical tag portion and the guard tag value not satisfying a match condition to indicate a fault condition. 
 
     
     
       16. A non-transitory, computer-readable storage device storing a computer program for controlling a host data processing apparatus to provide an instruction execution environment for execution of instructions of target program code, comprising:
 address translation program logic configured to perform a translation of a virtual address comprising a virtual tag portion and a virtual address portion into a physical address comprising a physical tag portion and a physical address portion, the physical address portion identifying a memory location to which access is required and the physical tag portion indicating whether to perform a predetermined memory operation, and the address translation program logic comprising: 
 address tag translation program logic configured to perform a translation of the virtual tag portion into the physical tag portion, 
 wherein the address translation program logic is configured to select the translation to be performed by the address tag translation circuitry in dependence on the virtual address portion, and 
 wherein the virtual tag portion and the virtual address portion are non-overlapping portions of the virtual address, and the physical tag portion and the physical address portion are non-overlapping portions of the physical address; and 
 memory system program logic configured to receive the physical address and to access the memory location identified by the physical address portion, wherein the memory system program logic is responsive to reception of the physical address, when a predetermined part of the physical tag portion has a predetermined value, to perform the predetermined memory operation, 
 wherein the predetermined memory operation is a guard tag comparison of the physical tag portion against a guard tag value associated with the memory location and the memory system is responsive to the physical tag portion and the guard tag value not satisfying a match condition to indicate a fault condition.