Vertical semiconductor device and method for fabricating the same

Abstract

A semiconductor device includes: an alternating stack that is disposed over a lower structure and includes gate electrodes and dielectric layers which are staked alternately; a memory stack structure that includes a channel layer extending to penetrate through the alternating stack, and a memory layer surrounding the channel layer; a source contact layer in contact with a lower outer wall of the vertical channel layer and disposed between the lower structure and the alternating stack; a source contact plug spaced apart from the memory stack structure and extending to penetrate through the alternating stack; and a sealing spacer suitable for sealing the gate electrodes and disposed between the source contact plug and the gate electrodes. The sealing spacer has an etch resistance that is different from an etch resistance of the dielectric layers.

What is claimed is: 
     
       1. A method for fabricating a semiconductor device, comprising:
 forming a source sacrificial layer over a lower structure; 
 forming a multi-layer stack in which dielectric layers and sacrificial layers are alternately stacked over the source sacrificial layer; 
 forming a memory stack structure that includes a channel layer and a memory layer, the memory stack structure extending to penetrate through the multi-layer stack and the source sacrificial layer; 
 forming a vertical contact recess that is spaced apart from the memory stack structure and extends to penetrate through the multi-layer stack and the source sacrificial layer; 
 exposing a lower outer wall of the channel layer by selectively removing the source sacrificial layer and a lower portion of the memory layer of the memory stack structure through the vertical contact recess; 
 forming a source contact layer that surrounds the lower outer wall of the channel layer; 
 replacing the sacrificial layers of the multi-layer stack with gate electrodes to form an alternating stack; 
 forming a sealing spacer to seal a sidewall of the vertical contact recess over the source contact layer and the gate electrodes; and 
 forming a source contact plug in the vertical contact recess, 
 wherein the sealing spacer includes a stack of a layer of carbon-free silicon oxide and a layer of carbon-containing silicon oxide, and the carbon-containing silicon oxide is in direct contact with the source contact plug. 
 
     
     
       2. The method of  claim 1 , wherein the carbon-containing silicon oxide having a wet-etch resistance greater than that of the dielectric layers. 
     
     
       3. The method of  claim 1 , wherein the carbon-free silicon oxide includes SiO 2 . 
     
     
       4. The method of  claim 1 , wherein the carbon-containing silicon oxide includes SiCO, and a carbon content of SiCO is less than a silicon content and an oxygen content. 
     
     
       5. The method of  claim 1 , wherein an outer wall of the source contact plug is surrounded by the sealing spacer, and
 wherein the sealing spacer extends vertically to cover the gate electrodes, the dielectric layers, and the source contact layer, the gate electrodes and the dielectric layers being stacked vertically. 
 
     
     
       6. The method of  claim 1 , wherein the sealing spacer includes one or more protrusions extending in a specific direction to seal one or more ends of the gate electrodes, respectively, the specific direction being perpendicular to a direction in which the gate electrodes and the dielectric layers are stacked. 
     
     
       7. The method of  claim 1 , wherein the sealing spacer has a thickness of approximately in a range from 50 Å to 100 Å. 
     
     
       8. The method of  claim 1 , wherein the semiconductor device further comprises:
 a lower source layer between the lower structure and the source contact layer; and 
 an upper source layer between the alternating stack and the source contact layer, 
 wherein each of the upper source layer and the lower source layer include a semiconductor material. 
 
     
     
       9. The method of  claim 1 , wherein the source contact plug includes:
 a silicon-containing material pattern that fills a lower portion of the vertical contact recess; 
 a metal-containing material pattern disposed over the silicon-containing material, and 
 a barrier material layer disposed between the silicon-containing material and the metal-containing material. 
 
     
     
       10. The method of  claim 1 , further comprising:
 a liner layer between the alternating stack and the source contact layer, 
 wherein the liner layer and the carbon-containing silicon oxide include the same material. 
 
     
     
       11. The method of  claim 10 , wherein the liner layer and the carbon-containing silicon oxide include SiCO. 
     
     
       12. The method of  claim 10 , wherein the dielectric layers of the alternating stack include a bottom dielectric layer, the remaining dielectric layers of the alternating stack disposed over the bottom dielectric layer, the bottom dielectric layer having a thickness thinner than that of each of the remaining dielectric layers. 
     
     
       13. The method of  claim 1 , further comprising forming a lower source layer over the lower structure, the source sacrificial layer disposed over the lower source layer,
 wherein forming the sealing spacer comprises:
 forming a sealing layer over the dielectric layers, the gate electrodes, and the source contact layer, and the lower source layer; and 
 removing a portion of the sealing layer to expose the lower source layer. 
 
 
     
     
       14. The method of  claim 1 , further comprising:
 forming a lower source layer over the lower structure; 
 forming a first liner layer over the lower source layer; 
 forming a second liner layer over the source sacrificial layer; and 
 forming an upper source layer over the second liner layer, 
 wherein the source sacrificial layer disposed between the first liner layer and the second liner layer, and 
 wherein the multi-layer stack disposed on the upper source layer. 
 
     
     
       15. The method of  claim 14 , wherein the first liner layer, or the second liner layer, or both include a silicon oxide or a SiCO. 
     
     
       16. The method of  claim 14 , wherein the first liner layer includes a silicon oxide, and the second liner layer includes SiCO. 
     
     
       17. The method of  claim 1 , further comprising:
 forming a lower source layer over the lower structure; 
 forming a first liner layer over the lower source layer; and 
 forming a second liner layer over the source sacrificial layer, 
 wherein the source sacrificial layer disposed between the first liner layer and the second liner layer, 
 wherein the multi-layer stack disposed on the second liner layer, and 
 wherein the first liner layer is formed of a silicon oxide, and the second liner layer is formed of SiCO. 
 
     
     
       18. A method for fabricating a semiconductor device, comprising:
 forming a first multi-layer stack including a first liner layer, a second liner and a source sacrificial layer disposed between the first liner layer and the second liner layer; 
 forming a second multi-layer stack including dielectric layers and sacrificial layers over the first multi-layer stack; 
 forming a vertical contact recess extending through the second multi-layer stack and the source sacrificial layer; 
 replacing the source sacrificial layer with a source contact layer; 
 forming a sealing spacer on sidewall of the vertical contact recess; 
 replacing the sacrificial layers with conductive layers; and 
 forming a source contact plug in the vertical contact recess, 
 wherein the sealing spacer includes a stack of a layer of SiO 2  and a layer of SiCO, and the SiCO is in direct contact with the source contact plug. 
 
     
     
       19. The method of  claim 18 , further comprising:
 after forming the second multi-layer stack, 
 forming a memory stack structure that includes a channel layer and a memory layer, the memory stack structure extending to penetrate through the second multi-layer stack and the source sacrificial layer. 
 
     
     
       20. The method of  claim 18 , wherein forming the source contact plug in the vertical contact recess comprising:
 forming a silicon-containing material pattern; 
 forming a barrier material layer over the silicon-containing material pattern; and 
 forming a metal-containing material pattern over the barrier material.