Semiconductor chip stack structure, semiconductor package, and method of manufacturing the same

Abstract

A semiconductor chip stack includes first and second semiconductor chips. The first chip includes a first semiconductor substrate having an active surface and an inactive surface, a first insulating layer formed on the inactive surface, and first pads formed in the first insulating layer. The second semiconductor chip includes a second semiconductor substrate having an active surface and an inactive surface, a second insulating layer formed on the active surface, second pads formed in the second insulating layer, a polymer layer formed on the second insulating layer, UBM patterns buried in the polymer layer; and buried solders formed on the UBM patterns, respectively, and buried in the polymer layer. A lower surface of the buried solders is coplanar with that of the polymer layer, the buried solders contact the first pads, respectively, at a contact surface, and a cross-sectional area of the buried solders is greatest on the contact surface.

What is claimed is: 
     
       1. A semiconductor chip stack structure comprising:
 a first semiconductor chip comprising: 
 a first semiconductor substrate having an active surface and a non-active surface opposite to the active surface; 
 a first semiconductor device layer formed on the active surface and including a circuit pattern; 
 a first rear surface insulating layer formed on the non-active surface; 
 a plurality of first rear surface pads formed at a same level as the first rear surface insulating layer; 
 a first front surface insulating layer formed on the first semiconductor device layer and spaced apart from the first semiconductor substrate with the first semiconductor device layer interposed therebetween; 
 a plurality of first front surface pads formed at a same level as the first front surface insulating layer; 
 a plurality of first through electrodes configured to pass through the first semiconductor substrate and the first semiconductor device layer and to be electrically connected to the plurality of first rear surface pads, respectively, and the plurality of first front surface pads, respectively; 
 a first polymer layer formed on the first front surface insulating layer; 
 a plurality of first under bump metallurgy (UBM) patterns buried in the first polymer layer; and 
 a plurality of first buried solders formed on the plurality of first UBM patterns, respectively, and buried in the first polymer layer; and 
 a second semiconductor chip comprising: 
 a second semiconductor substrate having an active surface and a non-active surface opposite to the active surface; 
 a second semiconductor device layer formed on the active surface of the second semiconductor substrate and including a circuit pattern; 
 a second front surface insulating layer formed on the second semiconductor device layer and spaced apart from the second semiconductor substrate with the second semiconductor device layer interposed therebetween; 
 a plurality of second front surface pads formed at a same level as the second front surface insulating layer; 
 a second polymer layer formed on the second front surface insulating layer; 
 a plurality of second UBM patterns buried in the second polymer layer; and 
 a plurality of second buried solders formed on the plurality of second UBM patterns, respectively, and buried in the second polymer layer, 
 wherein the second semiconductor chip is on the first semiconductor chip; 
 wherein a lower surface of the plurality of second buried solders is coplanar with a lower surface of the second polymer layer, the lower surface of the second polymer layer is in contact with the first rear surface insulating layer, and the plurality of second buried solders contact the plurality of first rear surface pads, respectively, 
 wherein a horizontal cross-sectional area of each of the plurality of second buried solders is greatest on a contact surface with the first rear surface pad, 
 wherein the horizontal cross-sectional area is less than a horizontal cross-sectional area of the first rear surface pad, 
 wherein each of the plurality of second buried solders comprises a first portion having a horizontal cross-sectional area that is constant and a second portion having a horizontal cross-sectional area that changes, and 
 wherein the first portion and the second portion of each of the plurality of second buried solders include a same material. 
 
     
     
       2. The semiconductor chip stack structure of  claim 1 , wherein
 the horizontal cross-sectional area of the second portion increases as a distance from the contact surface with the first rear surface pad decreases. 
 
     
     
       3. The semiconductor chip stack structure of  claim 1 , wherein
 a rate of change of the horizontal cross-sectional area of the second portion in a first direction perpendicular to the active surface of the second semiconductor substrate is constant. 
 
     
     
       4. The semiconductor chip stack structure of  claim 1 , wherein
 a rate of change of the horizontal cross-sectional area of the second portion in a first direction perpendicular to the active surface of the second semiconductor substrate decreases as a distance from the contact surface with the first rear surface pad decreases. 
 
     
     
       5. The semiconductor chip stack structure of  claim 1 , wherein
 a rate of change of the horizontal cross-sectional area of the second portion in a first direction perpendicular to the active surface of the second semiconductor substrate increases as a distance from the contact surface with the first rear surface pad increases. 
 
     
     
       6. The semiconductor chip stack structure of  claim 1 , wherein
 a pitch of the plurality of second buried solders is no more than 20 μm. 
 
     
     
       7. The semiconductor chip stack structure of  claim 1 , wherein
 a maximum horizontal width of each of the plurality of second buried solders is no more than 15 μm. 
 
     
     
       8. The semiconductor chip stack structure of  claim 1 , wherein
 a maximum horizontal width of each of the plurality of second buried solders is less than a horizontal width of respective ones of the plurality of first rear surface pads. 
 
     
     
       9. The semiconductor chip stack structure of  claim 1 ,
 wherein each of the plurality of second buried solders is spaced apart from each side surfaces surface of each of the plurality of first rear surface pads. 
 
     
     
       10. The semiconductor chip stack structure of  claim 1 , further comprising a molding layer horizontally surrounding the first semiconductor chip, and the second semiconductor chip
 wherein a lateral surface of the first polymer layer is coplanar with a lateral surface of a device layer of the first semiconductor chip and a lateral surface of the second polymer layer is coplanar with a lateral surface of a device layer of the second semiconductor chip, and 
 wherein the molding layer in contact with the lateral surface of the first polymer layer and the lateral surface of the second polymer layer. 
 
     
     
       11. A semiconductor chip stack structure comprising a first semiconductor chip and a second semiconductor chip on the first semiconductor chip:
 the first semiconductor chip comprising: 
 a first semiconductor substrate having an active surface and a non-active surface opposite to the active surface; 
 a first semiconductor device layer formed on the active surface and including a circuit pattern; 
 a first rear surface insulating layer formed on the non-active surface; 
 a plurality of first rear surface pads formed at a same level as the first rear surface insulating layer; 
 a first front surface insulating layer formed on the first semiconductor device layer and spaced apart from the first semiconductor substrate with the first semiconductor device layer interposed therebetween; 
 a plurality of first front surface pads formed at a same level as the first front surface insulating layer; 
 a plurality of first through electrodes configured to pass through the first semiconductor substrate and the first semiconductor device layer and to be electrically connected to the plurality of first rear surface pads, respectively, and the plurality of first front surface pads, respectively; 
 a first polymer layer formed on the first front surface insulating layer; 
 a plurality of first under bump metallurgy (UBM) patterns buried in the first polymer layer; and 
 a plurality of first buried solders formed on the plurality of first UBM patterns, respectively, and buried in the first polymer layer; and 
 the second semiconductor chip comprising: 
 a second semiconductor substrate having an active surface and a non-active surface opposite to the active surface; 
 a second semiconductor device layer formed on the active surface of the second semiconductor substrate and including a circuit pattern; 
 a second front surface insulating layer formed on the second semiconductor device layer and spaced apart from the second semiconductor substrate with the second semiconductor device layer interposed therebetween; 
 a plurality of second front surface pads formed at a same level as the second front surface insulating layer; 
 a second polymer layer formed on the second front surface insulating layer; 
 a plurality of second UBM patterns buried in the second polymer layer; and 
 a plurality of second buried solders formed on the plurality of second UBM patterns, respectively, and buried in the second polymer layer, 
 wherein a lower surface of the plurality of second buried solders is coplanar with a lower surface of the second polymer layer, the lower surface of the second polymer layer is in contact with the first rear surface insulating layer, 
 wherein the plurality of second buried solders contact the plurality of first rear surface pads, respectively, 
 wherein each of the plurality of second buried solders comprises a first portion having a horizontal cross-sectional area that is constant and a second portion having a horizontal cross-sectional area that changes, 
 wherein the first portion and the second portion of each of the plurality of second buried solders include a same material, and 
 wherein the horizontal cross-sectional area of the second portion of each of the plurality of second buried solders increases as a distance from a contact surface with the first rear surface pad decreases, and the horizontal cross-sectional area of each of the plurality of second buried solders is less than a horizontal cross-sectional area of the first rear surface pad. 
 
     
     
       12. The semiconductor chip stack structure of  claim 11 , wherein
 the first semiconductor chip includes a logic chip, and the second semiconductor chip include memory chips. 
 
     
     
       13. The semiconductor chip stack structure of  claim 11 , wherein
 the first semiconductor chip comprises a plurality of external connection terminals formed at an opposite side of the second semiconductor chip from the active surface, and 
 wherein a width of the plurality of external connection terminals is greater than a width the plurality of second buried solders. 
 
     
     
       14. The semiconductor chip stack structure of  claim 13 , wherein
 each of the plurality of external connection terminals has a width of no less than 20 μm. 
 
     
     
       15. The semiconductor chip stack structure of  claim 11 , wherein
 a pitch of the plurality of second buried solders is no more than 20 μm.