Semiconductor memory device

Abstract

A semiconductor memory device, includes: a first region including a memory cell array; and a second region including a peripheral circuit. The second region includes a semiconductor substrate having a first surface and a second surface. The semiconductor substrate includes: a semiconductor region between the first and second surfaces; an n-type semiconductor region provided on the first surface and higher in donor concentration than the semiconductor region; a damaged region provided on the second surface; and a p-type semiconductor region provided between the damaged region and the n-type semiconductor region, closer to the second surface than the n-type semiconductor region in a direction from the first surface toward the second surfaces of the semiconductor substrate, and higher in acceptor concentration than the semiconductor region.

What is claimed is: 
     
       1. A semiconductor memory device, comprising:
 a first region including a memory cell array; and 
 a second region including a peripheral circuit, 
 the second region comprising a semiconductor substrate having a first surface and a second surface, 
 the semiconductor substrate including:
 a semiconductor region between the first and second surfaces; 
 an n-type semiconductor region provided on the first surface and higher in donor concentration than the semiconductor region; 
 a damaged region provided on the second surface; and 
 a p-type semiconductor region provided between the damaged region and the n-type semiconductor region, closer to the second surface than the n-type semiconductor region in a direction from the first surface toward the second surface of the semiconductor substrate, and higher in acceptor concentration than the semiconductor region. 
 
 
     
     
       2. The device according to  claim 1 , wherein the semiconductor substrate has a thickness of 2 μm or more and 10 μm or less. 
     
     
       3. The device according to  claim 1 , wherein the donor concentration in the n-type semiconductor region is 1×10 16  cm −3  or more and 1×10 20  cm −3  or less. 
     
     
       4. The device according to  claim 1 , wherein the acceptor concentration in the p-type semiconductor region is 1×10 16  cm −3  or more and 1×10 20  cm −3  or less. 
     
     
       5. The device according to  claim 1 , wherein the p-type semiconductor region extends along the second surface in the entire second region. 
     
     
       6. A semiconductor memory device comprising:
 a wiring board; 
 a chip stack including a plurality of memory chips, the plurality of memory chips being stacked above the wiring board; and 
 an insulation resin layer covering the chip stack, 
 at least one chip selected from the group consisting of the plurality of memory chips comprising a first region including a memory cell array and a second region including a peripheral circuit, 
 the second region comprising a semiconductor substrate having a first surface and a second surface, and 
 the semiconductor substrate including:
 a semiconductor region between the first and second surfaces; 
 an n-type semiconductor region provided on the first surface and higher in donor concentration than the semiconductor region; 
 a damaged region provided on the second surface and being in contact with the insulation resin layer; and 
 a p-type semiconductor region provided between the damaged region and the n-type semiconductor region, closer to the second surface than the n-type semiconductor region in a direction from the first surface toward the second surface of the semiconductor substrate, and higher in acceptor concentration than the semiconductor region. 
 
 
     
     
       7. The device according to  claim 6 , wherein the semiconductor substrate has a thickness of 2 μm or more and 10 μm or less. 
     
     
       8. The device according to  claim 6 , wherein the donor concentration in the n-type semiconductor region is 1×10 16  cm −3  or more and 1×10 20  cm −3  or less. 
     
     
       9. The device according to  claim 6 , wherein the acceptor concentration in the p-type semiconductor region is 1×10 16  cm −3  or more and 1×10 20  cm −3  or less. 
     
     
       10. The device according to  claim 6 , wherein the p-type semiconductor region extends along the second surface in the entire second region.