Quadrature voltage-controlled oscillator (QVCO) with improved phase noise and quadrature imbalance trade-off

Abstract

Apparatus and methods for generating multiple oscillating signals. An example circuit generally includes a first voltage-controlled oscillator (VCO) circuit and a second VCO circuit having a differential bias input coupled to a differential output of the first VCO circuit. At least one of the first VCO circuit or the second VCO circuit generally includes: a pair of cross-coupled transistors comprising a first transistor and a second transistor, a first inductive element coupled between a first node and the drain of the first transistor, a second inductive element coupled between the first node and the drain of the second transistor, a third transistor having a drain coupled to the drain of the first transistor and having a source coupled to a second node, and a fourth transistor having a drain coupled to the drain of the second transistor and having a source coupled to the second node.

What is claimed is: 
     
       1. A circuit for generating oscillating signals, comprising:
 a first voltage-controlled oscillator (VCO) circuit; and 
 a second VCO circuit having a differential bias input coupled to a differential output of the first VCO circuit, at least one of the first VCO circuit or the second VCO circuit comprising:
 a pair of cross-coupled transistors comprising a first transistor and a second transistor, wherein the first transistor has a gate coupled to a drain of the second transistor and wherein the second transistor has a gate coupled to a drain of the first transistor; 
 a first inductive element coupled between a first node and the drain of the first transistor; 
 a second inductive element coupled between the first node and the drain of the second transistor; 
 a third transistor having a drain coupled to the drain of the first transistor and having a source coupled to a second node; and 
 a fourth transistor having a drain coupled to the drain of the second transistor and having a source coupled to the second node, wherein the third transistor and the fourth transistor are p-type transistors. 
 
 
     
     
       2. The circuit of  claim 1 , further comprising a resistive element coupled between the first node and the second node. 
     
     
       3. The circuit of  claim 2 , wherein the resistive element is tunable. 
     
     
       4. The circuit of  claim 1 , wherein the first transistor and the second transistor are n-type transistors. 
     
     
       5. The circuit of  claim 1 , wherein a differential output of the second VCO circuit is cross-coupled to a differential bias input of the first VCO circuit. 
     
     
       6. The circuit of  claim 5 , wherein:
 the drain of the first transistor and the drain of the second transistor are coupled to the differential output of the first VCO circuit; 
 a gate of the third transistor is coupled to a negative output of the differential output of the second VCO circuit; and 
 a gate of the fourth transistor is coupled to a positive output of the differential output of the second VCO circuit. 
 
     
     
       7. The circuit of  claim 5 , wherein:
 the drain of the first transistor and the drain of the second transistor are coupled to the differential output of the second VCO circuit; 
 a gate of the third transistor is coupled to a positive output of the differential output of the first VCO circuit; and 
 a gate of the fourth transistor is coupled to a negative output of the differential output of the first VCO circuit. 
 
     
     
       8. The circuit of  claim 5 , wherein the differential bias input of the first VCO circuit is configured to receive an in-phase differential signal, wherein the first VCO circuit is configured to generate a quadrature differential signal on the differential output of the first VCO circuit, and wherein the second VCO circuit is configured to receive the quadrature differential signal on the differential bias input of the second VCO circuit and to generate a complementary in-phase differential signal on the differential output of the second VCO circuit. 
     
     
       9. The circuit of  claim 1 , further comprising:
 a current source coupled between a power supply rail and the second node; and 
 a plurality of varactors coupled between the drain of the first transistor and the drain of the second transistor, wherein sources of the first transistor and the second transistor are coupled to a reference potential node. 
 
     
     
       10. The circuit of  claim 1 , wherein the first inductive element and the second inductive element are part of a center-tapped inductive element and wherein the first node is a tap of the center-tapped inductive element. 
     
     
       11. A method for generating a plurality of oscillating signals, comprising:
 generating a first oscillating signal with a first voltage-controlled oscillator (VCO) circuit; 
 biasing a second VCO circuit with the first oscillating signal; and 
 generating a second oscillating signal with the second VCO circuit, at least one of the first VCO circuit or the second VCO circuit comprising:
 a pair of cross-coupled transistors comprising a first transistor and a second transistor, wherein the first transistor has a gate coupled to a drain of the second transistor and wherein the second transistor has a gate coupled to a drain of the first transistor; 
 a first inductive element coupled between a first node and the drain of the first transistor; 
 a second inductive element coupled between the first node and the drain of the second transistor; 
 a third transistor having a drain coupled to the drain of the first transistor and having a source coupled to a second node; and 
 a fourth transistor having a drain coupled to the drain of the second transistor and having a source coupled to the second node, wherein the third transistor and the fourth transistor are p-type transistors. 
 
 
     
     
       12. The method of  claim 11 , further comprising tuning a resistive element coupled between the first node and the second node. 
     
     
       13. The method of  claim 11 , further comprising biasing the first VCO circuit with an inverted version of the second oscillating signal. 
     
     
       14. The method of  claim 13 , wherein the inverted version of the second oscillating signal is an in-phase differential signal, wherein the first oscillating signal is a quadrature differential signal, and wherein the second oscillating signal is a complementary in-phase differential signal. 
     
     
       15. The method of  claim 11 , wherein the first transistor and the second transistor are n-type transistors. 
     
     
       16. The method of  claim 11 , further comprising adjusting a voltage applied to a plurality of varactors to adjust a frequency of at least one of the first oscillating signal or the second oscillating signal, respectively, the plurality of varactors being coupled between the drain of the first transistor and the drain of the second transistor in the at least one of the first VCO circuit or the second VCO circuit.