Remote register updates

Abstract

Examples described herein provide for a first core to map a measurement of packet processing activity and operating parameters so that a second core can access the measurement of packet processing activity and potentially modify an operating parameter of the first core. The second core can modify operating parameters of the first core based on the measurement of packet processing activity. The first and second cores can be provisioned on start-up with a common key. The first and second cores can use the common key to encrypt or decrypt measurement of packet processing activity and operating parameters that are shared between the first and second cores. Accordingly, operating parameters of the first core can be modified by a different core while providing for secure modification of operating parameters.

What is claimed is: 
     
       1. An apparatus comprising:
 an interface and 
 a central processing unit (CPU) coupled to the interface, the CPU comprising a first core and a second core, wherein:
 the first core is to copy a measurement of processing activity performed using the first core and share the measurement of processing activity with the second core, 
 the second core to selectively modify a level of activity of the first core based on the measurement of processing activity, and 
 the first core is different from the second core. 
 
 
     
     
       2. The apparatus of  claim 1 , wherein the measurement of processing activity comprises a branch hit / miss measurement. 
     
     
       3. The apparatus of  claim 1 , wherein the processing activity comprising packet processing and wherein the first core is to perform packet processing based on Data Plane Development Kit (DPDK) or OpenDataPlane (ODP) and is to poll a network interface to identify at least one received packet at a rate according to a frequency setting of the first core. 
     
     
       4. The apparatus of  claim 1 , wherein the second core is to adjust a frequency of operation of the first core based on a level of the measurement of processing activity. 
     
     
       5. The apparatus of  claim 1 , wherein to copy the measurement of processing activity performed using the first core and share the measurement of processing activity with the second core, the first core is to utilize a key to encrypt the measurement of processing activity performed using the first core and share the encrypted measurement of processing activity with the second core. 
     
     
       6. The apparatus of  claim 5 , wherein to utilize a key to encrypt the measurement of processing activity performed using the first core and share the encrypted measurement of processing activity with the second core comprises one or more of:
 the first core is to encrypt at least a portion of content of performance and operations registers using the key; 
 the first core is to copy the encrypted at least the portion of content of the performance and operations registers into a shared buffer region; 
 the second core is to read the encrypted at least the portion of content of the performance and operations registers from the shared buffer region; or 
 the second core is to decrypt the encrypted at least the portion of content of the performance and operations registers using the key. 
 
     
     
       7. The apparatus of  claim 1 , wherein:
 the measurement of processing activity includes a portion of content of a performance monitoring unit (PMU) register of the first core, 
 the PMU register includes a branch hit / miss measurement, 
 the second core is to execute a power management process to determine a network interface activity level based on the branch hit / miss measurement, and 
 to selectively modify a level of activity of the first core based on the measurement of processing activity, the second core is to selectively modify a frequency of operation of the first core based on the branch hit / miss measurement. 
 
     
     
       8. The apparatus of  claim 1 , wherein:
 to selectively modify a level of activity of the first core based on the measurement of processing activity, the second core is to perform one or more of the following:
 selectively modify a frequency of operation of the first core by modification of a portion of content a Power and Thermal Management (PTM) register of the first core, 
 encrypt the modified portion of content of the PTM, or 
 copy the encrypted modified portion of content of the PTM into a shared buffer region, and 
 
 the first core is to perform one or more of the following:
 copy the encrypted modified portion of content of the PTM from the shared buffer region, 
 decrypt the encrypted modified portion of content of the PTM, or 
 poll a network interface for received packets according to the frequency of operation specified in the modified portion of content of the PTM. 
 
 
     
     
       9. The apparatus of  claim 1 , wherein:
 the second core is to use a secure enclave to decrypt the measurement of processing activity using a key. 
 
     
     
       10. The apparatus of  claim 1 , wherein the first core is to share the measurement of processing activity with the second core using a register address space and the second core is to modify a level of activity of the first core using the register address space. 
     
     
       11. The apparatus of  claim 1 , further comprising:
 a network interface communicatively coupled to the first core. 
 
     
     
       12. The apparatus of  claim 1 , comprising a data center, server, rack, host computer, or compute sled and wherein the data center, server, rack, host computer, or compute sled comprises the interface and the CPU. 
     
     
       13. The apparatus of  claim 1 , comprising at least one memory coupled to the interface. 
     
     
       14. A method comprising:
 configuring first and second cores with a common key, wherein the first and second cores encrypt or decrypt shared content using the common key and 
 configuring at least one operating parameter and performance measurement of the first core using the second core by: 
 copying the at least one operating parameter and performance measurement of the first core to a shared buffer accessible by the second core. 
 
     
     
       15. The method of  claim 14 , wherein the performance measurement comprises a branch hit / miss measurement. 
     
     
       16. The method of  claim 14 , wherein the copying the at least one operating parameter and performance measurement of the first core to a shared buffer accessible by the second core comprises the first core encrypting the at least one operating parameter and performance measurement of the first core and storing the encrypted at least one operating parameter and performance measurement of the first core in the shared buffer. 
     
     
       17. The method of  claim 14 , comprising:
 the second core performing: modifying at least one operating parameter, encrypting the at least one operating parameter, and copying the encrypted at least one modified operating parameter into the shared buffer and 
 the first core adjusting its operating based on the encrypted at least one modified operating parameter. 
 
     
     
       18. A system comprising:
 a network interface; 
 a register; 
 a first core to perform processing of a packet received by the network interface and copy at least one operating parameter and performance measurement of the first core to the register; and 
 a second core, wherein to adjust a polling rate for received packets applied by the first core, the second core is to adjust the at least one operating parameter from the register. 
 
     
     
       19. The system of  claim 18 , wherein the first core is to encrypt the at least one operating parameter and performance measurement of the first core using a key and store the encrypted at least one operating parameter and performance measurement of the first core into the register. 
     
     
       20. The system of  claim 19 , wherein the second core is to decrypt at least one operating parameter and performance measurement of the first core stored in the register using a copy of the key. 
     
     
       21. The system of  claim 19 , wherein:
 the second core is to determine whether to adjust the polling rate for received packets based on at least one performance measurement and 
 based on a determination to adjust the polling rate for received packets, the second core is to modify a portion of the at least one operating parameter and store the modified portion of the at least one operating parameter into the register. 
 
     
     
       22. The system of  claim 19 , wherein:
 the first core is to decrypt the at least one operating parameter and performance measurement of the first core from the register and store the decrypted at least one operating parameter and performance measurement of the first core to a register of the first core and 
 the first core is to poll for received packets at the network interface based on the decrypted at least one operating parameter and performance measurement of the first core from the register. 
 
     
     
       23. An apparatus comprising:
 an interface and a central processing unit (CPU) coupled to the interface, the CPU comprising a first core and a second core, wherein:
 the first core is to copy a measurement of processor activity performed using the first core and share the measurement of processor activity with the second core, 
 the second core to selectively request the first core to modify a level of activity of the first core based on the measurement of processor activity, and 
 the first core is different from the second core. 
 
 
     
     
       24. The apparatus of  claim 23 , wherein the level of activity comprises a frequency of operation or rate of polling a network interface. 
     
     
       25. The apparatus of  claim 23 , comprising at least one memory coupled to the interface. 
     
     
       26. The apparatus of  claim 23 , wherein the processor activity comprises packet processing associated with Data Plane Development Kit (DPDK) or OpenDataPlane (ODP) compatible packet processing. 
     
     
       27. An apparatus comprising:
 a first core and a second core, wherein 
 the first core comprises circuitry, when operational, to share encrypted performance monitoring data of the first core with the second core and 
 the second core comprises circuitry, when operational, to decrypt the encrypted performance monitoring data and to adjust power consumption of the first core based on the decrypted performance monitoring data. 
 
     
     
       28. The apparatus of  claim 27 , wherein the performance monitoring data comprises data from one or more performance monitoring unit (PMU) registers. 
     
     
       29. The apparatus of  claim 27 , wherein the first core and second core are to share a key for use by the circuitry of the second core to decrypt the encrypted performance monitoring data. 
     
     
       30. The apparatus of  claim 27 , wherein the encrypted performance monitoring data is stored in a memory and/or register accessible to the circuitry of the second core.