US11704068B2ActiveUtilityA1
Apparatus and method for scheduling operations performed in plural memory devices included in a memory system
Est. expiryMar 31, 2041(~14.7 yrs left)· nominal 20-yr term from priority
Inventors:Ji Hoon Lee
G06F 3/0659G06F 3/0604G06F 3/0613G06F 3/0631G06F 3/0656G06F 3/0688G06F 3/0658G06F 3/0679G06F 3/064G06F 3/061G06F 12/0607G06F 13/1642
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Claims
Abstract
A memory system includes a plurality of memory groups capable of performing a data input/output operation, and a controller configured to divide an operation subject to a data input/output command into at least one unit operation corresponding to the plurality of memory groups, and assign the at least one unit operation to plural queues corresponding to the respective memory groups, based on first information regarding operation statuses of the plurality of memory groups and second information regarding available resources.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1. A memory system, comprising:
a plurality of memory groups capable of performing a data input/output operation; and
a controller configured to:
divide an operation subject to a data input/output command into at least one unit operation corresponding to the plurality of memory groups, and
assign the at least one unit operation to plural queues corresponding to the respective memory groups, based on first information regarding operation statuses of the plurality of memory groups and second information regarding available resources,
wherein the controller is further configured to determine the first information based on at least one first unit operation being performed in the plurality of memory groups and at least one second unit operation which is assigned to the plurality of memory groups and included in the plural queues.
2. The memory system according to claim 1 , wherein the controller determines the first information by:
assigning different weights to the at least one first unit operation and the at least one second unit operation according to a type of unit operation,
scoring operational burdens for the respective memory groups based on the weights assigned to the at least one first unit operation and the at least one second unit operation, and
comparing the scored operational burdens with a reference.
3. The memory system according to claim 1 ,
wherein each of the plurality of memory groups comprises plural non-volatile memory cells storing a data item and a buffer memory for temporarily storing the data item, and
wherein each of the plurality of memory groups independently performs the at least one unit operation in an interleaving mode.
4. The memory system according to claim 1 , wherein the controller is configured to adjust or change an assignment sequence of the at least one unit operation, based on the first information and the second information, before assigning the at least one unit operation to the plural queues.
5. A memory system, comprising:
a plurality of memory groups capable of performing a data input/output operation; and
a controller configured to:
divide an operation subject to a data input/output command into at least one unit operation corresponding to the plurality of memory groups,
assign the at least one unit operation to plural queues corresponding to the respective memory groups, based on first information regarding operation statuses of the plurality of memory groups and second information regarding available resources, and
allocate at least one resource for the at least one unit operation,
wherein, when a quantity of unit operations is greater than a quantity of resources, the controller is configured to assign the at least one unit operation to a pending queue which is distinguishable from the plural queues.
6. The memory system according to claim 5 , wherein the quantity of resources is equal to a quantity of metadata for data input/output, which is allocated by a flash translation layer or a flash interface layer included in the controller.
7. The memory system according to claim 5 , wherein the quantity of resources is equal to a quantity of threads which the controller is capable of controlling.
8. A method for operating a memory system, the method comprising:
dividing an operation subject to a data input/output command into at least one unit operation corresponding to a plurality of memory groups;
determining first information regarding operation statuses of the plurality of memory groups, based on at least one first unit operation being performed in the plurality of memory groups and at least one second unit operation which is assigned to the plurality of memory groups and included in plural queues; and
assigning the at least one unit operation to the plural queues corresponding to the respective memory groups, based on second information regarding available resources and the first information.
9. The method according to claim 8 , wherein the determining the first information comprises:
assigning different weights to the at least one first unit operation and the at least one second unit operation according to a type of unit operation;
scoring operational burdens for the respective memory groups based on the weights assigned to the at least one first unit operation and the at least one second unit operation; and
comparing the scored operational burdens with a reference.
10. The method according to claim 8 , wherein the at least one unit operation is independently performed by each of the plurality of memory groups in an interleaving mode.
11. The method according to claim 8 , wherein the at least one unit operation is unassigned to the plural queues when a quantity of unit operations is greater than a quantity of resources.
12. The method according to claim 11 , further comprising assigning the unassigned unit operation to a pending queue.
13. The method according to claim 8 , further comprising adjusting or changing an assignment sequence of the at least one unit operation based on the first information and the second information, before assigning the at least one unit operation to the plural queues.
14. A controller in communication with a plurality of memory groups, which are capable of performing a data input/output operation via plural data paths, the controller comprising at least one processor, at least one memory and a logic, at least a portion of the logic comprised in hardware,
wherein the logic is configured to:
establish, in the at least one memory, a first region for temporarily storing first operation data regarding an operation subject to a command input from an external device and a second region for temporarily storing second operation data regarding at least one second unit operation scheduled to be performed in the plurality of memory groups; and
generate the second operation data from the first operation data, based on second information regarding available resources and first information regarding operation statuses of the plurality of memory groups,
wherein the logic is further configured to determine the first information based on at least one first unit operation being performed in the plurality of memory groups and at least one second unit operation of the second operation data stored in the second region and included in the plural queues.
15. The controller according to claim 14 , wherein the logic determines the first information by:
assigning different weights to the at least one first unit operation and the at least one second unit operation according to a type of unit operation,
scoring operational burdens for the respective memory groups based on the weights assigned to the at least one first unit operation and the at least one second unit operation, and
comparing the scored operational burdens with a reference.
16. The controller according to claim 14 , wherein the logic is further configured to:
establish, in the at least one memory, a third region for temporarily storing third operation data regarding at least one pending operation or at least one pending unit operation which is not included in the second operation data; and
generate the third operation data from the first operation information, based on the first and second information.
17. The controller according to claim 16 , wherein the logic is further configured to adjust or change a sequence of the second operation data or the third operation data while generating the second operation data to be stored in the second region or the third operation data to be stored in the third region based on the first operation data stored in the first region.Cited by (0)
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