Memory device including on-die-termination circuit

Abstract

A memory device includes; a first memory chip including a first on-die Termination (ODT) circuit comprising a first ODT resistor, a second memory chip including a second ODT circuit comprising a second ODT resistor, at least one chip enable signal pin that receives at least one chip enable signal, wherein the at least one chip enable signal selectively enables at least one of the first memory chip and the second memory chip, and an ODT pin commonly connected to the first memory chip and the second memory chip that receives an ODT signal, wherein the ODT signal defines an enable period for at least one of the first ODT circuit and the second ODT circuit, and in response to the ODT signal and the at least one chip enable signal, one of the first ODT resistor and the second ODT resistor is enabled to terminate a signal received by at least one of the first memory chip and the second memory chip.

What is claimed is: 
     
       1. An operating method of a storage device including a NAND flash memory device and a controller configured to control the NAND flash memory device, the method comprising:
 transmitting a command and an address, via an input/output line, from the controller to the NAND flash memory device; 
 transmitting an on-die Termination (ODT) signal, via a single ODT signal line, from the controller to the NAND flash memory device including a first memory chip including a first ODT circuit, a second memory chip including a second ODT circuit, a third memory chip including a third ODT circuit, and a fourth memory chip including a fourth ODT circuit, the ODT signal defining an enable period for at least one of the first to fourth ODT circuits; 
 transmitting a first chip enable signal, via a first chip enable signal line, from the controller to the first and second memory chips; 
 transmitting a second chip enable signal, via a second chip enable signal line, from the controller to the third and fourth memory chips; and 
 providing a first ODT resistor or a second ODT resistor by the at least one of the first to fourth ODT circuits, in response to the ODT signal, at least one of the first and second chip enable signals, and the address. 
 
     
     
       2. The operating method of  claim 1 , wherein the providing of the first ODT resistor or the second ODT resistor comprises:
 providing the first ODT resistor by each of the first and second ODT circuits, in response to the ODT signal being enabled and the first chip enable signal being disabled, thereby the first and second ODT circuits being enabled to terminate a signal received by the first and second memory chips. 
 
     
     
       3. The operating method of  claim 1 , wherein the providing of the first ODT resistor or the second ODT resistor comprises:
 providing the first ODT resistor by each of the third and fourth ODT circuits, in response to the ODT signal being enabled, the first chip enable signal being enabled, and the second chip enable signal being disabled, thereby the third and fourth ODT circuits being enabled to terminate a signal received by the third and fourth memory chips; and 
 providing the second ODT resistor by the second ODT circuit, in response to the ODT signal being enabled, the first chip enable signal being enabled, the second chip enable signal being disabled, and the address indicating the first memory chip, thereby the second ODT circuit being enabled to terminate a signal received by the second memory chip. 
 
     
     
       4. The operating method of  claim 3 , further comprising:
 disabling the first ODT circuit, in response to the ODT signal being enabled, the first chip enable signal being enabled, the second chip enable signal being disabled, and the address indicating the first memory chip. 
 
     
     
       5. The operating method of  claim 1 , further comprising:
 communicating a signal, via a signal line, from the controller to the NAND flash memory device during an ODT period in which the ODT signal is enabled, thereby at least one of the first to fourth ODT circuits being enabled to terminate the signal. 
 
     
     
       6. The operating method of  claim 5 , wherein the signal is at least one of a data signal, a data strobe signal, and a read enable signal. 
     
     
       7. The operating method of  claim 5 , wherein the signal is a read enable signal, and
 wherein the communicating of the signal comprises: communicating the read enable signal being toggled at a first toggle frequency, from the controller to the NAND flash memory device during the ODT period, thereby the at least one of the first to fourth ODT circuits being enabled to terminate the read enable signal. 
 
     
     
       8. The operating method of  claim 5 , wherein the signal is a data strobe signal, and
 wherein the communicating of the signal comprises: transmitting the data strobe signal being toggled at a second toggle frequency, from the controller to the NAND flash memory device during the ODT period, thereby the at least one of the first to fourth ODT circuits being enabled to terminate the data strobe signal. 
 
     
     
       9. The operating method of  claim 1 , further comprising:
 transmitting at least one set feature command including information associated with an ODT resistance value of at least one of the first and second memory chips, from the controller to the NAND flash memory device. 
 
     
     
       10. A memory system comprising:
 a NAND flash memory device; and 
 a controller configured to control the memory device, 
 wherein the memory device comprises: 
 a first chip enable signal pin that receives a first chip enable signal; 
 a second chip enable signal pin that receives a second chip enable signal; 
 a first memory chip including a first on-die-termination (ODT) circuit and a second memory chip including a second ODT circuit, wherein the first memory chip and second memory chip are commonly connected to the first chip enable signal pin; 
 a third memory chip including a third ODT circuit and a fourth memory chip including a fourth ODT circuit, wherein the third memory chip and fourth memory chip are commonly connected to the second chip enable signal pin; and 
 an ODT pin that receives an ODT signal, wherein the first memory chip, the second memory chip, the third memory chip and the fourth memory chip are commonly connected to the ODT pin, 
 wherein in response to the ODT signal, the first ODT circuit uses a first ODT resistor to terminate a signal received by at least one of the first memory chip, the second memory chip, the third memory chip and the fourth memory chip, the second ODT circuit uses a second ODT resistor to terminate the signal, the third ODT circuit uses a third ODT resistor to terminate the signal, or the fourth ODT circuit uses a fourth ODT resistor to terminate the signal. 
 
     
     
       11. The memory system of  claim 10 , wherein in response to the ODT signal and the first chip enable signal being an enabled level, the first ODT circuit or the second ODT circuit in a selected one of the first and second memory chips is disabled. 
     
     
       12. The memory system of  claim 10 , wherein the controller is configured to:
 transmit the ODT signal, via a single ODT signal line, to the NAND flash memory device, in order to enable at least one of the first to fourth ODT circuits, 
 transmit the first chip enable signal, via a first chip enable signal line, to the first and second memory chips, and 
 transmit the second chip enable signal, via a second chip enable signal line, to the third and fourth memory chips. 
 
     
     
       13. The memory system of  claim 12 , wherein the controller is further configured to:
 transmit at least one set feature command including information associated with an ODT resistance value of at least one of the first to fourth memory chips, to the NAND flash memory device.