Memory bypass for error detection and correction

Abstract

Methods, systems, and devices for compressed logical-to-physical mapping for a memory bypass for error detection and correction are described. A memory device may include error detection and correction circuitry for detecting and correcting errors in data that is read from a memory array of the memory device. To reduce read latencies, the memory device may include bypass circuitry that enables it to transmit the data to the host device before or during error detection. If the memory device determines that the data is erroneous, the memory device may transmit an alert to the host device concurrently with or after transmitting the data. The memory device may perform error correction on the data and store corrected data in a register. Based on receiving an alert, the host device may issue one or more additional read commands to re-read the data from the memory bank or read the corrected data from the register.

What is claimed is: 
     
       1. An apparatus, comprising:
 a memory array; and 
 a control component coupled with the memory array and configured to cause the apparatus to:
 receive, from a host device, a read command associated with reading data from the memory array; 
 read the data from a bank of the memory array based at least in part on the read command; 
 transmit, to the host device concurrently with transmitting a first portion of the data to the host device and before transmitting a second portion of the data, an indication of an error status of the first portion of the data; 
 determine whether there is an error in a second portion of the data; and 
 transmit, after transmitting the indication of the error status and the first portion of the data and concurrently with transmitting the second portion of the data to the host device, an alert to the host device that there is the error in the second portion of the data. 
 
 
     
     
       2. The apparatus of  claim 1 , wherein the control component is further configured to cause the apparatus to:
 perform, based at least in part on determining that there is the error in the second portion of the data and after transmitting the second portion of the data to the host device, an error correction procedure on the second portion of the data to generate corrected data; and 
 store the corrected data in a register. 
 
     
     
       3. The apparatus of  claim 2 , wherein the control component is further configured to cause the apparatus to:
 receive, from the host device after transmitting the second portion of the data, a second read command associated with reading the second portion of the data from the memory array; 
 determine a location from which to read second data corresponding to the second portion of the data based at least in part on the second read command; 
 read the second data from the location based at least in part on determining the location; and 
 transmit the second data to the host device. 
 
     
     
       4. The apparatus of  claim 3 , wherein the location is associated with the bank of the memory array, and reading the second data from the location comprises reading the data from the bank of the memory array. 
     
     
       5. The apparatus of  claim 4 , wherein the control component is further configured to cause the apparatus to:
 determine, based at least in part on re-reading the second portion of the data from the bank of the memory array, whether there is a second error associated with re-reading the second portion of the data; and 
 transmit, concurrently with transmitting the second data, a second alert to the host device based at least in part on determining that there is the second error associated with re-reading the second portion of the data. 
 
     
     
       6. The apparatus of  claim 3 , wherein the control component is further configured to cause the apparatus to:
 identify a size of the second portion of the data based at least in part on receiving the second read command, wherein determining the location from which to read the data is based at least in part on the size of the second portion of the data. 
 
     
     
       7. The apparatus of  claim 2 , wherein the control component is configured to cause the apparatus to transmit the second portion of the data to the host device by transmitting the second portion of the data to the host device on a first conductive path, and wherein the control component is configured to cause the apparatus to concurrently transmit the alert to the host device by transmitting the alert to the host device on a second conductive path. 
     
     
       8. The apparatus of  claim 7 , wherein the register is coupled with the first conductive path. 
     
     
       9. The apparatus of  claim 1 , wherein the control component is further configured to cause the apparatus to:
 identify, before transmitting the alert to the host device, a configuration setting, wherein transmitting the alert to the host device is based at least in part on identifying the configuration setting. 
 
     
     
       10. The apparatus of  claim 1 , wherein the control component is further configured to cause the apparatus to:
 receive, from the host device before receiving the read command, a write command associated with writing first data to the memory array; and 
 write the first data to the memory array, wherein reading the data comprises reading a representation of the first data. 
 
     
     
       11. An electronic device, comprising:
 a memory array; 
 a first conductive path coupled with the memory array and configured to transmit data that is read from the memory array to a host device; 
 an error detection component having an input coupled with the memory array and with the first conductive path, the error detection component configured to:
 receive the data that is read from the memory array, 
 detect whether there is an error associated with the data that is read from the memory array, and 
 generate an alert based on detecting that there is the error associated with the data; 
 
 an error correction component coupled with an output of the error detection component and an input of a register, the error correction component configured to correct at least one error in the data to generate corrected data and transfer the corrected data to the register; and
 a second conductive path coupled with the error detection component and configured to receive the alert from the error detection component and transmit the alert to the host device in parallel with the first conductive path transmitting the data to the host device. 
 
 
     
     
       12. The electronic device of  claim 11 , wherein the register is coupled with the first conductive path for transmitting the corrected data to the host device. 
     
     
       13. The electronic device of  claim 11 , wherein the first conductive path comprises a 32-bit data bus configured to transmit at least a portion of the data to the host device. 
     
     
       14. The electronic device of  claim 11 , wherein the second conductive path is coupled with a pin of the memory array and is configured to provide the alert to the host device using the pin. 
     
     
       15. The electronic device of  claim 14 , wherein the pin comprises a data mask/invert (DMI) pin. 
     
     
       16. The electronic device of  claim 11 , further comprising:
 clock circuitry configured to generate a clock signal of the memory array for synchronizing operations of the memory array, wherein the memory array is configured to transmit the data and the alert in parallel based at least in part on detecting a single edge of the clock signal. 
 
     
     
       17. The electronic device of  claim 11 , wherein the first conductive path is coupled with a first bank of the memory array. 
     
     
       18. A non-transitory computer-readable medium storing code comprising instructions, which when executed by a processor of an electronic device, cause the electronic device to:
 receive, from a host device, a read command associated with reading data from a memory array of the electronic device; 
 read the data from a bank of the memory array based at least in part on the read command; 
 transmit, to the host device concurrently with transmitting a first portion of the data to the host device and before transmitting a second portion of the data, an indication of an error status of the first portion of the data; 
 determine whether there is an error in a second portion of the data; and 
 transmit, after transmitting the indication of the error status and the first portion of the data and concurrently with transmitting the second portion of the data to the host device, an alert to the host device that there is the error in the second portion of the data. 
 
     
     
       19. The non-transitory computer-readable medium of  claim 18 , wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to:
 perform, based at least in part on determining that there is the error in the second portion of the data and after transmitting the second portion of the data to the host device, an error correction procedure on the second portion of data to generate corrected data; and 
 store the corrected data in a register of the memory array. 
 
     
     
       20. The non-transitory computer-readable medium of  claim 19 , wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to:
 receive, from the host device after transmitting the second portion of the data, a second read command associated with reading the second portion of the data from the memory array; 
 determine a location in the memory array from which to read second data corresponding to the second portion of the data based at least in part on the second read command; 
 read the second data from the location based at least in part on determining the location; and 
 transmit the second data to the host device. 
 
     
     
       21. An apparatus, comprising:
 a memory array; and 
 a control component coupled with the memory array and configured to cause the apparatus to:
 receive, from a host device, a read command associated with reading data from the memory array; 
 read the data from a bank of the memory array based at least in part on the read command; 
 transmit the data to the host device based at least in part on reading the data; 
 determine whether there is an error associated with reading the data; 
 transmit, concurrently with transmitting the data to the host device, an alert to the host device based at least in part on determining that there is the error associated with reading the data; 
 perform, based at least in part on determining that there is the error associated with reading the data and after transmitting at least a portion of the data to the host device, an error correction procedure on the data to generate corrected data; 
 store the corrected data in a register; 
 receive, from the host device after transmitting the data, a second read command associated with reading the data from the memory array; 
 determine a location from which to read second data corresponding to the data based at least in part on the second read command, wherein the location is within the register; 
 read the second data from the location based at least in part on determining the location, wherein reading the second data from the location comprises reading the corrected data from the register; and 
 transmit the second data to the host device. 
 
 
     
     
       22. The apparatus of  claim 21 , wherein the second read command is a different command than the read command and the second read command indicates that the location is within the register. 
     
     
       23. A non-transitory computer-readable medium storing code comprising instructions, which when executed by a processor of an electronic device, cause the electronic device to:
 receive, from a host device, a read command associated with reading data from a memory array of the electronic device; 
 read the data from a bank of the memory array based at least in part on the read command; 
 transmit the data to the host device based at least in part on reading the data; 
 determine whether there is an error associated with reading the data; 
 transmit, concurrently with transmitting the data to the host device, an alert to the host device based at least in part on determining that there is the error associated with reading the data; 
 perform, based at least in part on determining that there is the error associated with reading the data and after transmitting at least a portion of the data to the host device, an error correction procedure on the data to generate corrected data; 
 store the corrected data in a register of the memory array; 
 receive, from the host device after transmitting the data, a second read command associated with reading the data from the memory array; 
 determine a location in the memory array from which to read second data corresponding to the data based at least in part on the second read command wherein the location is within the register of the memory array; 
 read the second data from the location based at least in part on determining the location, wherein reading the second data from the location comprises reading the corrected data from the register; and 
 transmit the second data to the host device. 
 
     
     
       24. The non-transitory computer-readable medium of  claim 23 , wherein the second read command is a different command than the read command and the second read command indicates that the location is within the register of the memory array.