Display panel and display device comprising cascaded shift registers

Abstract

Provided are a display panel and a display device. The display panel includes a driver circuit including N stages of cascaded shift registers, where N≥2. Each shift register includes a first control part and a second control part. The second control part includes a first control unit and a second control unit. The first control unit is configured to receive a signal of a preset node and a first output control signal and control a signal of a fourth node, where the preset node is one of a second node or a third node. A first output control signal received by a shift register at an M 1 -th stage is a signal of the preset node of a shift register at an M 2 -th stage, where 1≤M 1 ≤N, 1≤M 2 ≤N, 1≤|M 1 −M 2 |≤i, and 2≤i≤N−1.

What is claimed is: 
     
       1. A display panel, comprising:
 a driver circuit comprising N stages of cascaded shift registers, wherein N≥2, and each of the N stages of cascaded shift registers comprises: a first control part and a second control part; 
 wherein the first control part is configured to receive at least an input signal and controls a signal of a first node and a signal of a second node in response to at least a first clock signal, and the first control part is configured to receive a first voltage signal and a second voltage signal and controls a signal of a third node in response to a signal of the first node and a signal of the second node, wherein the first voltage signal is a low level signal, and the second voltage signal is a high level signal; and the second control part comprises a first control unit and a second control unit; 
 the first control unit is configured to receive a signal of a preset node and a first output control signal and control a signal of a fourth node, wherein the preset node is one of the second node or the third node; and 
 the second control unit is configured to receive a third voltage signal and generate an output signal in response to a signal of the fourth node, or the second control unit is configured to receive a fourth voltage signal and generate an output signal in response to a signal of a fifth node, wherein the fifth node, the second node and the third node are three independent nodes, the fifth node is directly electrically connected to one of the second node or the third node that is not the preset node, the third voltage signal is a low level signal, and the fourth voltage signal is a high level signal; 
 a first output control signal received by a shift register at an M 1 -th stage is a signal of the preset node of a shift register at an M 2 -th stage, wherein 1≤M 1 ≤N, 1≤M 2 ≤N,  1 ≤|M 1 −M 2 |≤i, and 2≤i≤N−1. 
 
     
     
       2. The display panel of  claim 1 , wherein during at least part of a time period during which a signal of the fourth node is a low level signal, each of a signal of the preset node and the first output control signal is a low level signal. 
     
     
       3. The display panel of  claim 1 , wherein a pulse period of the first clock signal is S 1 , and a width of a low level pulse of the output signal is S 2 , wherein S 2 =a×S 1 , and i≤2a. 
     
     
       4. The display panel of  claim 1 , wherein the first control unit comprises a first capacitor, wherein a first electrode plate of the first capacitor is configured to receive the first output control signal, and a second electrode plate of the first capacitor is connected to the fourth node. 
     
     
       5. The display panel of  claim 4 , wherein the first control unit further comprises a first gating unit, wherein one terminal of the first gating unit is connected to the preset node, another terminal of the first gating unit is connected to the fourth node, and a control terminal of the first gating unit is configured to receive a fifth voltage signal; and
 in a case where each of a signal of the preset node and the first output control signal is a low level signal, the fifth voltage signal is configured to control the first gating unit to be turned off. 
 
     
     
       6. The display panel of  claim 5 , wherein the first gating unit comprises a first transistor, wherein a source of the first transistor is connected to the preset node, a drain of the first transistor is connected to the fourth node, and a gate of the first transistor is configured to receive the fifth voltage signal; and
 in a case where each of a signal of the preset node and the first output control signal is a low level signal, the fifth voltage signal is configured to control the first transistor to be turned off. 
 
     
     
       7. The display panel of  claim 6 , wherein the first transistor is a P-type metal oxide semiconductor (PMOS) type transistor, the fifth voltage signal is a constant low level signal V, and |V|≤|VGL 1 |+|Vth|, wherein VGL 1  denotes the first voltage signal, and Vth denotes a threshold voltage of the first transistor. 
     
     
       8. The display panel of  claim 6 , wherein the fifth voltage signal and the first voltage signal are a same signal. 
     
     
       9. The display panel of  claim 4 , wherein the first control unit further comprises a second gating unit, wherein one terminal of the second gating unit is connected to the fourth node, another terminal of the second gating unit is configured to receive the first output control signal, and a control terminal of the second gating unit is connected to the preset node; and
 in a case where a signal of the preset node is a low level signal, the second gating unit is turned on. 
 
     
     
       10. The display panel of  claim 9 , wherein the second gating unit comprises a second transistor, wherein a source of the second transistor is configured to receive the first output control signal, a drain of the second transistor is connected to the fourth node, and a gate of the second transistor is connected to the preset node. 
     
     
       11. The display panel of  claim 1 , wherein in a case where the preset node is the third node and the input signal of each of the N stages of cascaded shift registers is a low level signal, the output signal is a low level signal. 
     
     
       12. The display panel of  claim 1 , wherein in a case where the preset node is the second node and the input signal of each of the N stages of cascaded shift registers is a high level signal, the output signal is a low level signal. 
     
     
       13. The display panel of  claim 1 , wherein in the N stages of cascaded shift registers of the driver circuit, a signal of the third node of the shift register at the M 1 -th stage is connected to an input signal terminal of a shift register at an (M 1 +1)-th stage and is used as an input signal of the shift register at the (M 1 +1)-th stage, wherein 1≤M 1 ≤N. 
     
     
       14. The display panel of  claim 1 , wherein the second control unit comprises a third transistor and a fourth transistor;
 a source of the third transistor is configured to receive the third voltage signal, a drain of the third transistor is connected to an output signal terminal, and a gate of the third transistor is connected to the fourth node; and 
 a source of the fourth transistor is configured to receive the fourth voltage signal, a drain of the fourth transistor is connected to the output signal terminal, and a gate of the fourth transistor is connected to the fifth node. 
 
     
     
       15. The display panel of  claim 1 , wherein the first control part comprises a third control unit, a fourth control unit, and a fifth control unit;
 the third control unit is configured to receive the input signal and control a signal of a sixth node in response to the first clock signal, wherein the sixth node is connected to the first node; 
 the fourth control unit is configured to receive the second voltage signal and control a signal of the second node in response to at least the input signal and a signal of the sixth node; and 
 the fifth control unit is configured to receive the first voltage signal and the second voltage signal and control a signal of the third node in response to a signal of the first node and a signal of the second node. 
 
     
     
       16. The display panel of  claim 1 , wherein an effective pulse time of a first clock signal received by the shift register at the M 1 -th stage and an effective pulse time of a first clock signal received by a shift register at an (M 1 +1)-th stage do not overlap. 
     
     
       17. The display panel of  claim 1 , wherein the first control part comprises a third control unit, a fourth control unit, and a fifth control unit;
 the third control unit is configured to receive the input signal and control a signal of a sixth node in response to the first clock signal, wherein the sixth node is connected to the first node; 
 the fourth control unit is configured to receive the first voltage signal and the second voltage signal and control a signal of the second node in response to a signal of the sixth node, the first clock signal, and a second clock signal; and 
 the fifth control unit is configured to receive the first voltage signal and the second voltage signal and control a signal of the third node in response to a signal of the first node and a signal of the second node. 
 
     
     
       18. The display panel of  claim 1 , wherein in the N stages of cascaded shift registers of the driver circuit, an output signal of a shift register at an M 3 -th stage is not used as a drive signal of a display region of the display panel, and an output signal of a shift register at remaining at least one stage is used as the drive signal of the display region of the display panel, wherein 1≤M 3 ≤N. 
     
     
       19. A display device, comprising a display panel, wherein the display panel comprises: a driver circuit comprising N stages of cascaded shift registers, wherein N≥2, and each of the N stages of cascaded shift registers comprises: a first control part and a second control part;
 wherein the first control part is configured to receive at least an input signal and controls a signal of a first node and a signal of a second node in response to at least a first clock signal, and the first control part is configured to receive a first voltage signal and a second voltage signal and controls a signal of a third node in response to a signal of the first node and a signal of the second node, wherein the first voltage signal is a low level signal, and the second voltage signal is a high level signal; and the second control part comprises a first control unit and a second control unit; 
 the first control unit is configured to receive a signal of a preset node and a first output control signal and control a signal of a fourth node, wherein the preset node is one of the second node or the third node; and 
 the second control unit is configured to receive a third voltage signal and generate an output signal in response to a signal of the fourth node, or the second control unit is configured to receive a fourth voltage signal and generate an output signal in response to a signal of a fifth node, wherein the fifth node, the second node and the third node are three independent nodes, the fifth node is directly electrically connected to one of the second node or the third node that is not the preset node, the third voltage signal is a low level signal, and the fourth voltage signal is a high level signal; 
 a first output control signal received by a shift register at an M 1 -th stage is a signal of the preset node of a shift register at an M 2 -th stage, wherein 1≤M 1 ≤N, 1≤M 2 ≤N, 1≤|M 1 −M 2 |≤i, and 2≤i≤N−1.