Display apparatus in which gate pulses are outputted sequentially to alternate sides of a gate line

Abstract

A display apparatus sequentially outputs gate pulses to one side and the other side of gate lines. The display apparatus includes a display panel provided with four non-display areas outside a display area, a gate driver provided in a first non-display area of the non-display areas, a data driver provided in the first non-display area, and a controller for controlling the gate driver and the data driver. Gate lines connected to connection lines extended from the gate driver are provided in a second direction different from a first direction in which the connection lines are provided. Gate pulses supplied from the gate driver to the gate lines through the connection lines are alternately output from a first side and a second side of the gate lines. The first side and the second side are divided from each other based on a center portion of the gate lines as a boundary.

What is claimed is: 
     
       1. A display apparatus, comprising:
 a display panel having a first non-display area outside a display area; 
 a gate driver provided in the first non-display area; 
 a data driver provided in the first non-display area; 
 a controller for controlling the gate driver and the data driver; 
 connection lines extended from the gate driver, the connection lines being provided in a first direction; and 
 gate lines connected to the connection lines, the gate lines being provided in a second direction different from the first direction, 
 wherein gate pulses supplied from the gate driver to the gate lines through the connection lines are alternately output from a first side and a second side of the gate lines, 
 the first side and the second side of the gate lines are divided from each other based on a center portion of the gate lines as a boundary, 
 the gate driver includes:
 an odd shift register including odd flip-flops driven in a second side direction from a first side direction of the gate driver; 
 an even shift register including even flip-flops driven in the first side direction from the second side direction of the gate driver; 
 a level shifter unit configured to amplify odd shift clocks and even shift clocks, which are sequentially transmitted from the odd shift register and the even shift register, respectively, and sequentially outputting the amplified odd shift clocks and the amplified even shift clocks; and 
 a buffer unit configured to sequentially output gate pulses amplified by the level shifter unit to the gate lines. 
 
 
     
     
       2. The display apparatus of  claim 1 , wherein first side connection lines of the connection lines, which are connected to the gate driver at the first side, are connected to the first side of the gate lines, and
 second side connection lines of the connection lines, which are connected to the gate driver at the second side, are connected to the second side of the gate lines. 
 
     
     
       3. The display apparatus of  claim 2 , wherein the first side connection lines are alternately connected to odd gate lines and even gate lines of the gate lines, and
 the second side connection lines are alternately connected to other odd gate lines and other even gate lines of the gate lines. 
 
     
     
       4. The display apparatus of  claim 2 , wherein the display panel is provided with first to (g)th connection lines connected to the gate driver and first to (g)th gate lines connected to the first to (g)th connection lines,
 the first side connection lines of the connection lines are connected to odd gate lines of the first to ((g/2)-1)th gate lines and even gate lines of the (g)th to ((g/2)+2)th gate lines, 
 the second side connection lines of the connection lines are connected to odd gate lines of ((g/2)+1)th to (g)th gate lines and even gate lines of (g/2)th to first gate lines, and 
 wherein ‘g’ is an even natural number. 
 
     
     
       5. The display apparatus of  claim 4 , wherein the first side connection lines are alternately connected to odd gate lines of the first to ((g/2)-1)th gate lines and even gate lines of the (g)th to ((g/2)+2)th gate lines, and
 the second side connection lines are alternately connected to odd gate lines of the ((g/2)+1)th to (g)th gate lines and even gate lines of the (g/2)th to first gate lines. 
 
     
     
       6. The display apparatus of  claim 1 , wherein the odd flip-flops are sequentially driven from the first side direction to the second side direction to sequentially output the odd shift clocks, and
 the even flip-flops are sequentially driven from the second side direction to the first side direction to sequentially output the even shift clocks. 
 
     
     
       7. The display apparatus of  claim 6 , wherein the odd flip-flops and the even flip-flops are alternately driven. 
     
     
       8. The display apparatus of  claim 6 , wherein odd gate pulses generated by the odd shift clocks are output to odd gate lines of the gate lines, and
 even gate pulses generated by the even shift clocks are output to even gate lines of the gate lines. 
 
     
     
       9. The display apparatus of  claim 1 , wherein the gate driver includes at least two gate driver integrated circuits, (ICs), each of the gate driver ICs including:
 the odd shift register; 
 the even shift register; 
 the level shifter unit; and 
 the buffer unit, 
 wherein the at least two gate driver Ics include first to (n)th gate driver Ics provided in the second side direction from the first side direction, 
 the first to (n)th gate driver Ics are driven by a start control signal transmitted from a gate driver IC adjacent thereto or the controller, and 
 wherein n is a natural number. 
 
     
     
       10. The display apparatus of  claim 9 , wherein an odd shift register provided in an (m)th gate driver IC is driven in accordance with an odd start control signal transmitted from an odd shift register provided in a (m−1)th gate driver IC,
 an even shift register provided in the (m−1)th gate driver IC is driven in accordance with an even start control signal transmitted from an even shift register provided in the (m)th gate driver IC, and 
 ‘m’ is less than or equal to ‘n’. 
 
     
     
       11. The display apparatus of  claim 1 , wherein two gate pulses continuously outputted to two connection lines provided in the center portion of the gate lines are outputted from the first side or outputted from the second side. 
     
     
       12. A display apparatus, comprising:
 a display panel having a display area and a non-display area, the non-display area being outside the display area; 
 a gate driver positioned in the non-display area; 
 gate lines including:
 odd gate lines extending in a second direction; and 
 even gate lines extending in the second direction; and 
 
 connection lines including:
 first side connection lines extending in a first direction different from the second direction, the first side connection lines being positioned on a first side of the gate lines; and 
 second side connection lines extending in the first direction, the second side connection lines being positioned on a second side of the gate lines, the second side and the first side of the gate lines being on opposite sides of a center portion of the gate lines; 
 
 wherein gate pulses supplied from the gate driver to the gate lines through the connection lines are alternately output from the first side and the second side of the gate lines; 
 wherein the gate lines include:
 a first gate line; 
 a fourth gate line; 
 a second gate line between the first gate line and the fourth gate line, the second gate line being adjacent the first gate line; and 
 a third gate line between the second gate line and the fourth gate line; 
 
 wherein the connection lines include:
 a first connection line connected to the first gate line; 
 a second connection line connected to the second gate line, the second connection line being a connection line nearest along the second direction to the first connection line among connection lines connected to the second gate line; 
 a third connection line connected to the third gate line; and 
 a fourth connection line connected to the fourth gate line; 
 
 wherein the first and third connection lines are on the first side, and the second and fourth connection lines are on the second side, 
 wherein the gate driver includes at least one gate driver integrated logic circuit (ILC), and 
 the gate driver ILC includes:
 an odd shift register including odd flip-flops driven in a second side direction from a first side direction of the gate driver; 
 an even shift register including even flip-flops driven in the first side direction from the second side direction of the gate driver; 
 a level shifter unit for amplifying odd shift clocks and even shift clocks, which are sequentially transmitted from the odd shift register and the even shift register, respectively, and for sequentially outputting the amplified odd shift clocks and the amplified even shift clocks; and 
 a buffer unit for sequentially outputting gate pulses amplified by the level shifter unit to the gate lines. 
 
 
     
     
       13. The display apparatus of  claim 12 , wherein, in operation, a second gate pulse is received by the second gate line between a first gate pulse being received by the first gate line and a third gate pulse being received by the third gate line. 
     
     
       14. The display apparatus of  claim 12 , wherein
 the first gate line and the third gate line receive odd gate pulses based on output of odd flip-flops of an odd shift register, and 
 the second gate line and the fourth gate line receive even gate pulses based on an output of even flip-flops of an even shift register. 
 
     
     
       15. The display apparatus of  claim 14 , wherein the odd flip-flops are on the first side, and the even flip-flops are on the second side. 
     
     
       16. A display apparatus, comprising:
 a display panel provided with at least one non-display areas outside a display area; 
 a gate driver including gate driver integrated circuit logic (ICL), the gate driver ICL including:
 an odd shift register including odd flip-flops driven in a second side direction from a first side direction of the gate driver; 
 an even shift register including even flip-flops driven in the first side direction from the second side direction of the gate driver; 
 a level shifter unit for amplifying odd shift clocks and even shift clocks, which are sequentially transmitted from the odd shift register and the even shift register, respectively, and for sequentially outputting the amplified odd shift clocks and the amplified even shift clocks; and 
 a buffer unit for sequentially outputting gate pulses amplified by the level shifter unit to the gate lines; 
 wherein, in operation, odd shift clocks and even shift clocks are sequentially transmitted from the odd shift register and the even shift register, respectively; 
 
 a data driver; 
 a controller for controlling the gate driver and the data driver, wherein the controller, the gate driver and the data driver are positioned on same side of the display panel; 
 connection lines extended from the gate driver, the connection lines being provided in a first direction; and 
 gate lines connected to the connection lines, the gate lines being provided in a second direction different from the first direction, wherein gate pulses supplied from the gate driver to the gate lines through the connection lines are alternately output from a first side and a second side of the gate lines, the gate lines including:
 a first gate line; and 
 a second gate line adjacent the first gate line; 
 
 the first side and the second side of the gate lines are divided from each other based on a center portion of the gate lines as a boundary; 
 wherein the connection lines include:
 a first connection line on the first side and connected to the first gate line; and 
 a second connection line on the second side and connected to the second gate line, the second connection line being a connection line nearest along the second direction to the first connection line among connection lines connected to the second gate line. 
 
 
     
     
       17. The display apparatus of  claim 16 , further comprising:
 a film overlapping a first non-display area of the at least one non-display areas; 
 wherein the gate driver and the data driver area positioned on the film. 
 
     
     
       18. The display apparatus of  claim 16 , wherein the controller is positioned in one of the at least one non-display areas, and the gate driver and the data driver are positioned in a same non-display area of the at least one non-display areas. 
     
     
       19. The display apparatus of  claim 16 , wherein the gate driver includes first to (n)th gate driver logic circuits provided in the second side direction from the first side direction, the first to (n)th gate driver logic circuits being driven by a start control signal transmitted from a respective gate driver IC adjacent thereto or the controller, wherein n is a natural number.