Semiconductor device and manufacturing method of semiconductor device

Abstract

A semiconductor device includes a cell array including a source structure, a peripheral circuit, an interconnection structure located between the cell array and the peripheral circuit and electrically coupled to the peripheral circuit, and a decoupling structure configured to prevent a coupling capacitor that occurs between the cell array and the interconnection structure.

What is claimed is: 
     
       1. A method of manufacturing a semiconductor device, the method comprising:
 forming a peripheral circuit; 
 forming a first interconnection structure that is electrically coupled to the peripheral circuit; 
 forming a decoupling structure having an electrically floating state over the first interconnection structure; and 
 forming a cell array over the decoupling structure. 
 
     
     
       2. The method of  claim 1 , wherein the forming of the decoupling structure comprises:
 forming a mold including an opening having a mesh shape over the first interconnection structure; and 
 forming a decoupling structure in the opening. 
 
     
     
       3. The method of  claim 1 , wherein the forming of the decoupling structure comprises:
 forming an etch stop layer over the first interconnection structure; 
 forming an interlayer insulating layer over the etch stop layer; 
 forming an opening in the interlayer insulating layer; and 
 forming the decoupling structure in the opening. 
 
     
     
       4. The method of  claim 1 , further comprising:
 forming a protective layer over the decoupling structure; and 
 forming an interlayer insulating layer over the protective layer. 
 
     
     
       5. The method of  claim 1 , wherein the decoupling structure has a mesh shape. 
     
     
       6. The method of  claim 1 , wherein the decoupling structure comprises:
 first conductive patterns; and 
 second conductive patterns crossing the first conductive patterns. 
 
     
     
       7. The method of  claim 1 , further comprising forming a second interconnection structure that is electrically coupled to the cell array. 
     
     
       8. The method of  claim 7 , wherein the second interconnection structure includes a contact plug passing through the decoupling structure and is electrically coupled to the first interconnection structure. 
     
     
       9. The method of  claim 7 , wherein the second interconnection structure includes a ground line electrically coupled to the decoupling structure. 
     
     
       10. A method of manufacturing a semiconductor device, the method comprising:
 forming a peripheral circuit; 
 forming a first interconnection structure that is electrically coupled to the peripheral circuit; 
 forming a decoupling structure having a mesh shape over the first interconnection structure; and 
 forming a cell array over the decoupling structure. 
 
     
     
       11. The method of  claim 10 , wherein the forming of the decoupling structure comprises:
 forming a mold including an opening having the mesh shape over the first interconnection structure; and 
 forming the decoupling structure in the opening. 
 
     
     
       12. The method of  claim 10 , wherein the forming of the decoupling structure comprises:
 forming an etch stop layer over the first interconnection structure; 
 forming an interlayer insulating layer over the etch stop layer; 
 forming an opening in the interlayer insulating layer; and 
 forming the decoupling structure in the opening. 
 
     
     
       13. The method of  claim 10 , further comprising:
 forming a protective layer over the decoupling structure; and 
 forming an interlayer insulating layer over the protective layer. 
 
     
     
       14. The method of  claim 10 , wherein the decoupling structure comprises:
 first conductive patterns; and 
 second conductive patterns crossing the first conductive patterns. 
 
     
     
       15. The method of  claim 10 , wherein the decoupling structure has an electrically floating state. 
     
     
       16. The method of  claim 10 , further comprising a second interconnection structure that is electrically coupled to the cell array. 
     
     
       17. The method of  claim 16 , wherein the second interconnection structure includes a contact plug passing through the decoupling structure and is electrically coupled to the first interconnection structure. 
     
     
       18. The method of  claim 16 , wherein the second interconnection structure includes a ground line electrically coupled to the decoupling structure.