US11731234B2ActiveUtilityA1

Method of double-side polishing semiconductor wafer

31
Assignee: SUMCO CORPPriority: Nov 2, 2016Filed: Oct 3, 2017Granted: Aug 22, 2023
Est. expiryNov 2, 2036(~10.3 yrs left)· nominal 20-yr term from priority
H10P 90/129H10P 90/124H10P 52/00H10P 90/123B24B 37/20B24B 37/042B24B 37/28H01L 21/02016H01L 21/02024B24B 37/08
31
PatentIndex Score
0
Cited by
14
References
4
Claims

Abstract

Provided is a method of double-side polishing a semiconductor wafer, which can suppress variation in the polishing quality by providing for changes in the polishing environment during polishing. The method of double-side polishing of a semiconductor wafer includes: a step of predetermining a criterion function for determining polishing tendencies of double-side polishing; a first step of starting double-side polishing of the semiconductor wafer under initial polishing conditions; a second step of while performing double-side polishing on the semiconductor wafer under the initial polishing conditions, calculating a value of the criterion function using the apparatus log data in a predetermined period of polishing in the first step, and setting on the double-side polishing apparatus polishing conditions obtained by adjusting the initial polishing conditions based on the value of the criterion function; and a third step of performing double-side polishing of the semiconductor wafer under the adjusted polishing conditions.

Claims

exact text as granted — not AI-modified
The invention claimed is: 
     
       1. A method of double-side polishing of a semiconductor wafer using a double-side polishing apparatus, comprising:
 a step of predetermining a criterion function for determining polishing tendencies of double-side polishing by performing multiple regression analysis based on a shape index of a plurality of semiconductor wafers having been subjected to double-side polishing using the double-side polishing apparatus and on apparatus log data of the double-side polishing apparatus in a last stage of polishing corresponding to the shape index; 
 a first step of starting double-side polishing of the semiconductor wafer under initial polishing conditions; 
 subsequent to the first step, a second step of while performing double-side polishing on the semiconductor wafer under the initial polishing conditions, calculating a value of the criterion function using apparatus log data obtained from a last stage of polishing in the first step, and setting on the double-side polishing apparatus polishing conditions obtained by adjusting the initial polishing conditions based on the value of the criterion function; and 
 subsequent to the second step, a third step of performing double-side polishing of the semiconductor wafer under the adjusted polishing conditions. 
 
     
     
       2. The method of double-side polishing a semiconductor wafer, according to  claim 1 , wherein a polishing time in the third step is based on the value of the criterion function. 
     
     
       3. The method of double-side polishing a semiconductor wafer, according to  claim 1 , wherein the adjusted polishing conditions involve adjustment of one or both of a rotation speed of plates of the double-side polishing apparatus and a load on the plates. 
     
     
       4. The method of double-side polishing a semiconductor wafer, according to  claim 1 , wherein the second step is started after the first step is completed.

Cited by (0)

No later patents cite this yet.

References (0)

No backward citations on record.