Memory with high-accuracy reference-free multi-inverter sense circuit and associated sensing method

Abstract

Disclosed is a memory structure with reference-free single-ended sensing. The structure includes an array of non-volatile memory (NVM) cells (e.g., resistance programmable NVM cells) and a sense circuit connected to the array via a data line and a column decoder. The sense circuit includes field effect transistors (FETs) connected in parallel between an output node and a switch and inverters connected between the data line and the gates of the FETs, respectively. To determine the logic value of a stored bit, the inverters are used to detect whether or not a voltage drop occurs on the data line within a predetermined period of time. Using redundant inverters to control redundant FETs connected to the output node increases the likelihood that the occurrence of the voltage drop will be detected and captured at the output node, even in the presence of process and/or thermal variations. Also disclosed is a sensing method.

What is claimed is: 
     
       1. A structure comprising:
 a data line; and 
 a sense circuit comprising:
 an output node; 
 a switch; 
 multiple pull-down field effect transistors connected in parallel between the output node and the switch; and 
 multiple inverters, wherein an input of each inverter is connected to the data line and an output of each inverter is connected to a gate of a corresponding one of the multiple pull-down field effect transistors, 
 
 wherein the switch comprises a pull-down transistor connecting the sense circuit to ground, 
 wherein the pull-down transistor of the switch turns on for a predetermined period of time in response to a sense enable signal, 
 wherein at an end of the predetermined period of time an output voltage on the output node is at one of a first voltage level and a second voltage level that is greater than the first voltage level, 
 wherein the output voltage is at the first voltage level when a voltage drop on the data line within the predetermined period of time causes at least one of the multiple inverters to switch output states from low to high so that at least one of the multiple pull-down field effect transistors turns on and pulls down the output voltage, and 
 wherein the output voltage is at the second voltage level when all of the multiple pull down field effect transistors remain off. 
 
     
     
       2. The structure of  claim 1 , further comprising a latch connected to the output node. 
     
     
       3. The structure of  claim 1 , wherein the multiple pull-down field effect transistors are each smaller than the pull-down transistor of the switch. 
     
     
       4. The structure of  claim 1 , further comprising:
 an array of memory cells arranged in columns and rows; 
 wordlines for the rows, wherein each wordline for each row is connected to all the memory cells in the row; 
 bitlines for the columns, wherein each bitline for each column is connected to all of the memory cells in the column; 
 source lines for the columns, wherein each source line for each column is connected to all of the memory cells in the column; and 
 peripheral circuitry connected to the wordlines, the bitlines and the source lines, 
 wherein, during a read operation to determine a logic value of a stored bit in a specific memory cell at a specific row and a specific column, the peripheral circuitry causes a specific bitline for the specific column to be pre-charged and connected to the data line and further causes a wordline voltage to be applied to a specific wordline for the specific row such that, when the switch turns on for the predetermined period of time, the specific memory cell discharges a voltage on the specific bitline at a first rate if the stored bit has a first logic value and at a second rate that is slower than the first rate if the stored bit has a second logic value. 
 
     
     
       5. The structure of  claim 4 , wherein each memory cell in each column and each row comprises: an access transistor and a programmable resistor connected in series between a source line for the column and a bitline for the column, and wherein the access transistor has a gate connected to the wordline for the row. 
     
     
       6. The structure of  claim 5 , wherein the programmable resistor comprises any of a magnetic tunnel junction-type variable resistor, a phase change memory-type variable resistor, and a memristor. 
     
     
       7. The structure of  claim 4 , wherein each memory cell in each column and each row comprises: a threshold voltage programmable transistor between a source line for the column and a bitline for the column, and wherein the threshold voltage programmable transistor has a gate connected to the wordline for the row. 
     
     
       8. A structure comprising:
 a data line; and 
 a sense circuit comprising:
 an output node; 
 a first pull-down transistor; 
 three second pull-down transistors connected in parallel between the output node and the first pull-down transistor, wherein the first pull-down transistor is further connected to ground; and 
 three inverters, wherein an input of each inverter is connected to the data line and an output of each inverter is connected to a gate of a corresponding one of the three second pull-down transistors, 
 
 wherein the first pull-down transistor is connected between ground and the second pull-down transistors and is larger than the second pull-down transistors, 
 wherein the first pull-down transistor turns on for a predetermined period of time in response to a sense enable signal, 
 wherein at an end of the predetermined period of time an output voltage on the output node is at one of a first voltage level and a second voltage level that is greater than the first voltage level, 
 wherein the output voltage is at the first voltage level when a voltage drop on the data line within the predetermined period of time causes at least one of the three inverters to switch output states from low to high so that at least one of the three second pull-down transistors turns on and pulls down the output voltage, and 
 wherein the output voltage is at the second voltage level when all of the three second pull-down transistors remain off. 
 
     
     
       9. The structure of  claim 8 , further comprising a latch connected to the output node. 
     
     
       10. The structure of  claim 8 , further comprising:
 an array of memory cells arranged in columns and rows; 
 wordlines for the rows, wherein each wordline for each row is connected to all the memory cells in the row; 
 bitlines for the columns, wherein each bitline for each column is connected to all of the memory cells in the column; 
 source lines for the columns, wherein each source line for each column is connected to all of the memory cells in the column; and 
 peripheral circuitry connected to the wordlines, the bitlines and the source lines, 
 wherein, during a read operation to determine a logic value of a stored bit in a specific memory cell at a specific row and a specific column, the peripheral circuitry causes a specific bitline for the specific column to be pre-charged and connected to the data line and further causes a wordline voltage to be applied to a specific wordline for the specific row such that, when the first pull-down transistor turns on for the predetermined period of time, the specific memory cell discharges a voltage on the specific bitline at a first rate if the stored bit has a first logic value and at a second rate that is slower than the first rate if the stored bit has a second logic value. 
 
     
     
       11. The structure of  claim 10 , wherein each memory cell in each column and each row comprises: an access transistor and a programmable resistor connected in series between a source line for the column and a bitline for the column, and wherein the access transistor has a gate connected to the wordline for the row. 
     
     
       12. The structure of  claim 11 , wherein the programmable resistor comprises any of a magnetic tunnel junction-type variable resistor, a phase change memory-type variable resistor, and a memristor. 
     
     
       13. The structure of  claim 10 , wherein each memory cell in each column and each row comprises: a threshold voltage programmable transistor between a source line for the column and a bitline for the column, and wherein the threshold voltage programmable transistor has a gate connected to the wordline for the row. 
     
     
       14. A method comprising:
 accessing a memory structure comprising:
 a memory array comprising an array of memory cells; 
 a data line connected to the memory array; and 
 a sense circuit comprising:
 an output node; 
 a switch; 
 multiple field effect transistors connected in parallel between the output node and the switch; and 
 multiple inverters, wherein each inverter is connected between the data line and a gate of a corresponding one of the multiple field effect transistors; and 
 
 performing a read operation comprising: 
 
 turning on the switch for a predetermined period of time; and 
 sensing an output voltage on the output node at an end of the predetermined period of time, 
 wherein at the end of the predetermined period of time the output voltage on the output node is at one of a first voltage level and a second voltage level that is greater than the first voltage level, and 
 wherein the output voltage is at the first voltage level at the end of the predetermined period of time when a voltage drop on the data line causes at least one of the multiple inverters to switch output states so that at least one of the multiple field effect transistors turns on and pulls the output voltage down to the first voltage level from the second voltage level. 
 
     
     
       15. The method of  claim 14 ,
 wherein the memory cells in the array are arranged in columns and rows; 
 wordlines for the rows, wherein each wordline for each row is connected to all the memory cells in the row; 
 bitlines for the columns, wherein each bitline for each column is connected to all of the memory cells in the column; 
 source lines for the columns, wherein each source line for each column is connected to all of the memory cells in the column, 
 wherein the read operation determines a logic value of a stored bit in a specific memory cell at a specific row and a specific column, and 
 wherein the performing of the read operation further comprises: 
 pre-charging a specific bitline for the specific column; 
 connecting the specific bitline to the data line; and 
 applying a wordline voltage to a specific wordline for the specific row such that, when the switch turns on for the predetermined period of time, the specific memory cell discharges a voltage on the specific bitline at a first rate if the stored bit has a first logic value and at a second rate that is slower than the first rate if the stored bit has a second logic value. 
 
     
     
       16. The method of  claim 15 , wherein each memory cell in each column and each row comprises: an access transistor and a programmable resistor connected in a series between a source line for the column and a bitline for the column, and wherein the access transistor has a gate connected to the wordline for the row. 
     
     
       17. The method of  claim 16 , wherein the programmable resistor comprises any of a magnetic tunnel junction-type variable resistor, a phase change memory-type variable resistor, and a memristor. 
     
     
       18. The method of  claim 15 , wherein each memory cell in each column and each row comprises: a threshold voltage programmable transistor between a source line for the column and a bitline for the column, and wherein the threshold voltage programmable transistor has a gate connected to the wordline for the row.